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TMS320F28075: Using DMA with ADC Highest Interrupt Priority

Robert
Prodigy 90 points
Part Number: TMS320F28075

Hi there,

We are using the TMS320F28075 in our system for medical applications.

In our system we trigger with 40kHz SOC from all our ADC channels. The EOC triggers the ADCA1 interrupt which has the highest interrupt priority. Within this interrupt current control is implemented. At the moment we are reading the results of the registers from the ADC every time we enter the ADCA1 ISR. We are using ADCA/ADCB and use for each 7 channels.

For further improvements we are thinking about implementing the DMA controller instead we are reading the register in every ISR. Ideally, we do not have to read and validate our ADC results using DMA. But the problem we see, is that for validating we need to get the DMA_CHx interrupt which have a lower priority and therefore will slow down the system completely. That would be a killer. Another option would be using the Channel1 from DMA and keep transferring the ADC results into a destination address range and use the values without checking it. Therefore, we just trust that the DMA is faster than the CPU. I mean, thats not great, too.

Is our idea even feasible ? We are quite unsure and also surprised, since the DMA channel1 is supposed to be ideal for ADC applications. We are not the first ones, who face this problem :-)

Secondly, is it possible to transfer data using DMA from ADCA/ADCB into a destination range which is aligned? That should be possible using the burst, wrap and transfer sizes and step?

Thank you and best regards

Robert

  • 0
    TI__Guru* 80160 points

    Robert,

    Thanks for reaching out to the E2E.  In terms of lower priority, that will only take effect if there are multiple ISRs pending to the PIE controller, and then the order in the PIE table will dictate the order of operations.  If the DMA ISR comes with nothing else pending it will get serviced, and unless you re-enable ISRs inside the DMA ISR(nesting) they will get held off until the DMA ISR completes/returns.  Keep in mind that the DMA ISR doesn't impact the DMA transfer of data from the ADC to memory; it is just letting you know that operation is complete.  In this scenario you would disable the ADC ISR.

    If there is still a concern you could still use the DMA to transfer the results to memory, but keep using the ADC ISR to trigger the current control loop, you may need to poll the DMA to make sure it is complete before you start to access the data.  This will still save time saving off the results to memory.

    Depending on how many ADC results you need before starting your current control loop, this could save the time from multiple ADC ISRs before you begin processing the data.  Not sure if you are using the PPB(Post Processing Block) inside the ADC, that can save some CPU cycles as well to take care of some simple adder/subtractor type functions before the ADC results are stored.

    I do want to make you aware of an errata around the DMA/ADC https://www.ti.com/lit/pdf/sprz423 starting on page 9.

    The transfer you mention should be possible, but if you'd like to give me an example of what you are thinking of here I can see if there is a preferred method for burst/transfer/wrap.

    Best,

    Matthew