TMS320F280049: Unknown pwm pulse

Due to a holiday on account of Memorial Day, please expect a response on Wednesday.

Thanks.

Hi Xu,

Can you please share how you have initialized your epwm modules, including the action qualifier settings?

Best Regards,

Marlyn

Hi  Marlyn,

I use below function to initialize my epwm module:

void CLLLC_HAL_setupHRPWMinUpDownCountModeWithDeadBand(uint32_t base1,
float32_t pwmFreq_Hz,
float32_t pwmSysClkFreq_Hz,
float32_t red_ns,
float32_t fed_ns)
{
uint32_t pwmPeriod_ticks;
uint32_t dbFED_ticks, dbRED_ticks;

pwmPeriod_ticks = (uint32_t)((pwmSysClkFreq_Hz *
                               (float32_t)TWO_RAISED_TO_THE_POWER_SIXTEEN) /
                               (float32_t)pwmFreq_Hz) >> 1;
pwmPeriod_ticks = (pwmPeriod_ticks & 0xFFFFFF00);

dbRED_ticks = ((uint32_t)(red_ns *
                         (float32_t)TWO_RAISED_TO_THE_POWER_SIXTEEN *
                         ((float32_t)ONE_NANO_SEC) * pwmSysClkFreq_Hz * 2.0f));
dbRED_ticks = ( dbRED_ticks & 0xFFFFFE00);

dbFED_ticks = ((uint32_t)(red_ns *
                        (float32_t)TWO_RAISED_TO_THE_POWER_SIXTEEN *
                        ((float32_t)ONE_NANO_SEC) * pwmSysClkFreq_Hz * 2.0f));
dbFED_ticks = ( dbFED_ticks & 0xFFFFFE00);

//
// Time Base SubModule Registers
//
EPWM_setPeriodLoadMode(base1, EPWM_PERIOD_SHADOW_LOAD);
HWREG(base1 + HRPWM_O_TBPRDHR) = pwmPeriod_ticks;

EPWM_setTimeBaseCounter(base1, 0);
EPWM_setPhaseShift(base1, 0);
EPWM_setTimeBaseCounterMode(base1, EPWM_COUNTER_MODE_UP_DOWN);
EPWM_setClockPrescaler(base1, EPWM_CLOCK_DIVIDER_1, EPWM_HSCLOCK_DIVIDER_1);

//
// Counter Compare Submodule Registers
// set duty 50% initially
//
pwmPeriod_ticks_temp = pwmPeriod_ticks * Duty_Set;
HWREG(base1 + HRPWM_O_CMPA) = pwmPeriod_ticks - pwmPeriod_ticks_temp;//pwmPeriod_ticks >> 1;

//
// set as shadow mode
//
EPWM_setCounterCompareShadowLoadMode(base1, EPWM_COUNTER_COMPARE_A,
EPWM_COMP_LOAD_ON_CNTR_ZERO_PERIOD);

//
// set as shadow mode
//
EPWM_setCounterCompareShadowLoadMode(base1, EPWM_COUNTER_COMPARE_B,
EPWM_COMP_LOAD_ON_CNTR_ZERO_PERIOD);

HWREG(base1 + HRPWM_O_CMPB) = pwmPeriod_ticks_temp;//pwmPeriod_ticks >> 1;

EPWM_disableCounterCompareShadowLoadMode(base1, EPWM_COUNTER_COMPARE_C);

EALLOW;
//
// Clear AQCTLA, B and Deadband settings settings
//
HWREGH(base1 + EPWM_O_AQCTLA) = 0x0000;
HWREGH(base1 + EPWM_O_AQCTLB) = 0x0000;

HWREGH(base1 + EPWM_O_DCBCTL) = 0x0000;
EDIS;

//
// Action Qualifier SubModule Registers
// CTR = CMPA@UP , xA set to 1
//
EPWM_setActionQualifierAction(base1, EPWM_AQ_OUTPUT_A ,
EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);

//
// CTR = CMPA@Down , xA set to 0
//
EPWM_setActionQualifierAction(base1, EPWM_AQ_OUTPUT_A ,
EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA);

//
// Active high complementary PWMs - Set up the deadband
//

EPWM_setRisingEdgeDelayCountShadowLoadMode(base1,
EPWM_RED_LOAD_ON_CNTR_ZERO);
EPWM_setFallingEdgeDelayCountShadowLoadMode(base1,
EPWM_FED_LOAD_ON_CNTR_ZERO);
EPWM_setDeadBandCounterClock(base1, EPWM_DB_COUNTER_CLOCK_HALF_CYCLE);

EPWM_setDeadBandDelayMode(base1, EPWM_DB_RED, true);
EPWM_setDeadBandDelayMode(base1, EPWM_DB_FED, true);
EPWM_setRisingEdgeDeadBandDelayInput(base1, EPWM_DB_INPUT_EPWMA);
EPWM_setFallingEdgeDeadBandDelayInput(base1, EPWM_DB_INPUT_EPWMA);
EPWM_setDeadBandDelayPolarity(base1, EPWM_DB_FED,
EPWM_DB_POLARITY_ACTIVE_LOW);
EPWM_setDeadBandDelayPolarity(base1, EPWM_DB_RED,
EPWM_DB_POLARITY_ACTIVE_HIGH);

HWREG(base1 + HRPWM_O_DBFEDHR) = dbFED_ticks;
HWREG(base1 + HRPWM_O_DBREDHR) = dbRED_ticks;

//
// Hi-res PWM
// MEP control on both edges.
//
HRPWM_setMEPEdgeSelect(base1, HRPWM_CHANNEL_A,
HRPWM_MEP_CTRL_RISING_AND_FALLING_EDGE);
HRPWM_setCounterCompareShadowLoadEvent(base1, HRPWM_CHANNEL_A,
HRPWM_LOAD_ON_CNTR_ZERO_PERIOD);
HRPWM_setMEPEdgeSelect(base1, HRPWM_CHANNEL_B,
HRPWM_MEP_CTRL_RISING_AND_FALLING_EDGE);
HRPWM_setCounterCompareShadowLoadEvent(base1, HRPWM_CHANNEL_B,
HRPWM_LOAD_ON_CNTR_ZERO_PERIOD);

HRPWM_setMEPControlMode(base1, HRPWM_CHANNEL_A, HRPWM_MEP_DUTY_PERIOD_CTRL);
HRPWM_setMEPControlMode(base1, HRPWM_CHANNEL_B, HRPWM_MEP_DUTY_PERIOD_CTRL);

HRPWM_setDeadbandMEPEdgeSelect(base1, HRPWM_DB_MEP_CTRL_RED_FED);

//
// Enable autoconversion
//
HRPWM_enableAutoConversion(base1);

//
// Turn on high-resolution period control.
//
HRPWM_enablePeriodControl(base1);

}

Hi Xu,

Thank you for sharing your code. What happens when you disable deadband? (Are you able to try this within your setup- just for debug)

Also, when are you enabling TBCLKSYNC? Do you disable it before you initialize your EPWMs?

Best Regards,

Marlyn

Hi Marlyn,

I use function"SysCtl_disablePeripheral(SYSCTL_PERIPH_CLK_TBCLKSYNC);" to disable TBCLKSYNC，after initilize PWM then use ”SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TBCLKSYNC);to enable TBCLKSYNC.

I try to modify below two sentence :

  EPWM_setDeadBandDelayMode(base1, EPWM_DB_RED, false);
  EPWM_setDeadBandDelayMode(base1, EPWM_DB_FED, false);

and found the unkown pulse at the beginning disappeard, but channel2 and channel 3 PWM not generated  (thery are complementary with channel1 and channel 4 respectively)waveform as below.  So am I right to disable DB use above method? 

best&regards

lucas

Hi Marlyn,

A new information, 

I think I have found the reason why channel2 and channel 3 PWM disapper,

 when I disable DB module ，I need add AQ configuration sentence about thease two channel as below，then all pwm are normal as below:

So it seems the DB module is the root cause of this issue?  Did my configuration have any problem about DB module in pervious code? If no problem,

how can we use DB and don‘t cause this issue? Thanks！

best & regards

lucas

Hi Lucas,

xu chunlei said:

So it seems the DB module is the root cause of this issue?  Did my configuration have any problem about DB module in pervious code? If no problem,

how can we use DB and don‘t cause this issue?

A suggestion for something that may work is using the trip-zone submodule to drive your outputs low using a software force. This would be during initialization (ie. before you configure deadband submodule). After you set TBCLKSYNC, remove the software forced trip condition. Let me know if this works for you.

Best Regards,

Marlyn

Hi Marln,

Follow your suggestion, I do as below，  step1 ： disable  TBCLKSYNC.  step2：use trip-zone  to drive pwm outputs low， step3： configurate pwm

step4： enable TBCLKSYNC， step5： clear trip-zone 。 but I found this issue still existed(waveform as below).

best&regards

lucas

Hello,

In this implementation did you setup TZA/TZB to drive the EPWMs low? 

I see in your initialization code that the time base counter is getting set to zero initially, does this change later in the application? 

Another thing to try is setting up the active high complementary pair within the deadband submodule, but keep the deadband values as 0. Does this still cause the issue? We need to narrow down what section of the code within the deadband submodule is causing the issue.

Also, its easier to debug without hrpwm. A suggestion I have would be to comment this out during the debug and once we isolate/correct the issue you can add that back in.

Best Regards,

Marlyn

Hi Marlyn,

(1)In this implementation did you setup TZA/TZB to drive the EPWMs low? 

I have add setup TZA/TZB to drive EPWM low, but this issue still existed,code as below:

(2)I see in your initialization code that the time base counter is getting set to zero initially, does this change later in the application? 

No, time base counter have no change later in application. 

(3) Another thing to try is setting up the active high complementary pair within the deadband submodule, but keep the deadband values as 0. Does this still cause the issue?

Yes, I tried this, enable DB but set value to 0, this issue still existed.

(4) Also I tried to disable HRPWM , like below,  this issue still existed.

It is very strange, Do you have any other idea for a try? Thanks!

best &regards

lucas

Hello,

xu chunlei said:

It is very strange, Do you have any other idea for a try? Thanks!

I think the remaining small pulses are due to the fact that the EPWMs are running when the trip zone is cleared (and it looks like CMPA is set to 0 initially). When the trip is cleared the EPWM resumes operation. Therefore, I think the solution is to disable the software trips inline with the EPWM counter. A suggestion for how to do this (I haven't necessarily tested it): setup a forced CBC trip instead of a one-shot trip and then setup an interrupt when TBCTR=PRD and clear the trip in the ISR - make sure that the CBC clear is setup for when time base counter = 0 (should be default). 

Please let me know if you have any questions about the above proposed method.

Best Regards,

Marlyn

Hi Marlyn,

I agree with your guess about the root cause，maybe due to the EPWMs are running when the trip zone is cleared

I have some not clear about your solution,

(1) you mean CMPA is set to 0? But in my initialization code ,CMPA is set to 50%period

(2)what is the trigger source of CBC？when enable CBC?

(3)when disable CBC？because I don't want to CBC continue work, after all configuration finished.

(4) use Epm1 or Epwm2 to configure this interrupt are all OK when TBCTR=PRD?

best &regards

lucas

Hello Lucas,

xu chunlei said:

(1) you mean CMPA is set to 0? But in my initialization code ,CMPA is set to 50%period

Sorry, I missed this line. The rest of the explanation should still apply though.

xu chunlei said:

(2)what is the trigger source of CBC？when enable CBC?

Actually, I think I may have an easier solution. You can keep what you have but instead of disabling the software trip after you enable TBCLKSYNC. Disable the software trip in an ISR for TBCTR=ZERO. Either EPWM1 or EPWM2 interrupt will work here. 

Best Regards,

Marlyn