TMS320F28388D: Doubt regarding the usage of SPI FIFO

Hi TI team,

I am trying to receive 20 bytes of data (Ten16 bit values) from master using SPI FIFO interrupts method in F2838D controller. 

Master Configurations (Not TI controller): Clock: 500KHz, Mode: 0 (Polarity & Phase both are zero), Data Width: 16

Slave Configurations (TI's F28388D): 500KHz, Mode: 0 (Polarity & Phase both are zero), Data Width: 16, FIFO Interrupt Level: 4, Interrupts activated: Receive Interrupt. The below image has the Slave Configurations.

In the below Rx ISR implementation, I am trying to read the complete data by monitoring the FIFO status until it goes to zero. 

 __interrupt void spiaRxFIFOISR(void)
{
    volatile uint16_t flags, chr, words, fifoStatus;
    uint16_t i = 0;
    printf("Entered InterruptServiceRoutine...: %d\n", i++);

    do
    {
        fifoStatus = SPI_getRxFIFOStatus(SPIA_slave_BASE);
        flags =  SPI_getInterruptStatus(SPIA_slave_BASE);

        if(SPI_getRxFIFOStatus(SPIA_slave_BASE))
        {
            chr = SPI_readDataBlockingFIFO(SPIA_slave_BASE);
            printf("The data is: %d\n",chr);
            ReceiveBuffer[NumCharsReceived++] = chr;
        }
    }while(SPI_getRxFIFOStatus(SPIA_slave_BASE) );

    SPI_resetRxFIFO(SPIA_slave_BASE);
    SPI_clearInterruptStatus(SPIA_slave_BASE, SPI_INT_RXFF);
    SPI_clearInterruptStatus(SPIA_slave_BASE, SPI_INT_RX_OVERRUN );
    Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP6);

}

The following image shows the capture of 4 signals of SPI probing in between the master and slave wires.

Questions:

1. Is it the proper way to read the data from SPI master, if not, could you please provide any resources where I can read all the data? (I already checked the SPI examples with FIFO, in the examples we are not monitoring any bits instead we are using a for loop).

2. If I set my FIFO interrupt level to 4, I am able to read 5 words of data (which is expected including FIFO 0th word) properly, but the interrupt is never coming to this ISR again to read the further data. In the ISR implementation, am I missing anything related to clearing the interrupts.?

3. What is the working/usage procedure/ flow for using the SPI FIFOs with interrupts?

Data sending from Master: 0x0000, 0x0001, 0x0002, 0x0003, 0x0004, 0x0005, 0x0006, 0x0007, 0x0008, 0x0009, 0x000A, 0x000B, 0x000C, 0x000D, 0x000E, 0x000F, 0x0010, 0x0011, 0x0012, 0x0013.

Data receiving in the slave with FIFO interrupt level 4: 0x0000, 0x0001, 0x0002, 0x0003, 0x0004.