TMS320F28377D: SPI FIFO mode

Hi Gobind,

Gobind Singh1 said:

When configured to FIFO mode (I did four settings: SPIFFENA=1, TXFIFO=1, RXFIFORESET=1, SPIFFTX.SPIRST=1), I write 8 bytes to SPITXBUF register, one-by-one without any delay in code. (Should I add delay here?)

Are you hoping to setup the FIFOs for both RX and TX? Additionally, are you planning on having interrupts enabled? 

I would suggest looking at the software examples within C2000Ware to cross-check your FIFO settings. We do have a SPI example that utilizes FIFOs and I believe the only thing that should change based on what you mentioned is the TXFILL and RXFILL levels. 

You should not need to add any delay between your TX writes.

Gobind Singh1 said:

But when 8 bytes are written together, I see same value read for all 8 bytes. I see that SPIFFRX.RXFFST value keeps decrementing as I read the values and it goes to zero in the end, but the values read are the same.

This is probably due to your setup of the FIFOs. Again, I would recommend referencing one of our C2000Ware examples and making sure the full FIFO configuration is setup correctly. 

Gobind Singh1 said:

Also, I could never see TXFFST set to any value other than zero in the Registers window. This could be because the data is sent on the pin as soon as it is written to SPITXBUF register. Please let me know if this understanding is correct and I will not be able to see any other value at TXFFST in the registers window

You should still see the value of TXFFST increment when you write to the buffer with back-to-back writes. 

Best Regards,

Marlyn

Thanks for the reply Marlyn.

Marlyn Rosales Castaneda20 said:

Are you hoping to setup the FIFOs for both RX and TX?

Yes, I want to setup FIFO for both RX and TX.

Marlyn Rosales Castaneda20 said:

Additionally, are you planning on having interrupts enabled? 

No. 

Marlyn Rosales Castaneda20 said:

I believe the only thing that should change based on what you mentioned is the TXFILL and RXFILL levels.

Aren't these levels only if I want to setup interrupts? 

Marlyn Rosales Castaneda20 said:

I would suggest looking at the software examples within C2000Ware to cross-check your FIFO settings. We do have a SPI example that utilizes FIFOs

I have seen the example and I think I have done settings as per that.

There are only 3 FIFO registers: 

SPIFFTX

SPIFFRX

SPIFFCT: Nothing to configure here as I dont want any delays.

I think I have configured all the writable bits of these two registers. Below are my settings, please let me know if there are more settings to be done.

My questions/problems are:

1. If FIFO is enabled for both TX and RX, should the SPI module wait for TXFFIL number of data to be written to SPITXBUF before it starts transmitting? And should TXFFST increment as I write to SPITXBUF.

If the answer is yes, I dont see that happening. Data is transmitted as soon as it is written to SPITXBUF and TXFFST is 0. I see RXFFST incrementing that means it has received data.

2. After RXFFST reaches 8, I start reading data from SPIRXBUF. I see that RXFFST decrements for each read but the data that I read is same everytime. So all the 8 bytes read are the same.

I only want to send 8 bytes of data, wait for RXFFST to be 8 and then read 8 bytes of data from SPIRXBUF. 

Thanks.

Gobind Singh

Hi Gobind,

Gobind Singh1 said:

I think I have configured all the writable bits of these two registers. Below are my settings, please let me know if there are more settings to be done.

Your configuration looks okay.

Gobind Singh1 said:

1. If FIFO is enabled for both TX and RX, should the SPI module wait for TXFFIL number of data to be written to SPITXBUF before it starts transmitting? And should TXFFST increment as I write to SPITXBUF.

There is a chance you don't see TXFFST if the data you write is getting immediately shifted to the shift register.

Gobind Singh1 said:

2. After RXFFST reaches 8, I start reading data from SPIRXBUF. I see that RXFFST decrements for each read but the data that I read is same everytime. So all the 8 bytes read are the same.

What value do you read back 8 times? The first byte you receive, last byte, etc.

Best Regards,

Marlyn

Hi Marlyn,

Marlyn Rosales Castaneda20 said:

What value do you read back 8 times? The first byte you receive, last byte, etc.

To find out this, when I stepped over each transmit and receive instructions, it worked all fine. Then I added wait after every write to the Tx buffer and it seems to work fine after that. The new code looks like the below:

But this does not look like a good solution. As you said in one of your previous replies that I should not need delay between writing to TXBUF register. 

Adding wait statements after every write to TXBUF makes it similar to non-buffered SPI. Is there any other solution?

Thank you.

Gobind Singh

Gobind Singh1 said:

To find out this, when I stepped over each transmit and receive instructions, it worked all fine.

To clarify, it worked only in step-over mode, not in continuous run mode. But after adding waits, it worked in continuous run mode also.

Gobind,

Gobind Singh1 said:

Adding wait statements after every write to TXBUF makes it similar to non-buffered SPI. Is there any other solution?

Thank you for sharing more details. Could you please let me know what data you are receiving back in the RX buffer? Previously you mentioned that it was the same every time but could you please describe the data that you are sending and the data you read? This will let me figure out what could be going on. Additionally, could you please share your full SPI initialization code?

Best Regards,

Marlyn

Hi Marlyn,

There are 8 bytes of data,

1. Bytes 1 to 7: Fault flags and fressness count

2. Byte 8: CRC

My spi init function is below, I have taken out RXFIL and TXFIL because they did not have any effect on my problem.

void initSpi()
{
spiRegs->SPICCR.bit.SPICHAR = 7;
spiRegs->SPICCR.bit.CLKPOLARITY = 0;
spiRegs->SPICTL.bit.CLK_PHASE = 0;
spiRegs->SPICTL.bit.MASTER_SLAVE = 1;
spiRegs->SPICTL.bit.TALK = 1;
spiRegs->SPIBRR.all = 9;

/* FIFO settings */
spiRegs->SPIFFTX.bit.SPIFFENA = 1;
spiRegs->SPIFFTX.bit.TXFIFO = 1;
spiRegs->SPIFFRX.bit.RXFIFORESET = 1;
spiRegs->SPIFFTX.bit.SPIRST = 1;

spiRegs->SPICCR.bit.SPISWRESET = 1;
spiRegs->SPIPRI.bit.FREE = 1;
}

Thanks

Gobind Singh

Hi Gobind,

In some of the code you provided you use spiRegs and in others SpicRegs. Is spiRegs initialized to point to SpicRegs?

Also, have you scoped the communication to verify that the TX data is getting sent out correctly (with no delay to writes to the TX buffer) and that you are getting the RX data that you expect going into the device?

Are you able to provide a simple testcase demonstrating the issue (maybe by modifying a C2000Ware example)?

Best Regards,

Marlyn