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Hi Experts,
F28022S is mass production on customer side. Customer have few question about those device, could you help on it? Thanks.
1. Background
| Issue description | Normal description |
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When the UVLO reset function enabled, when VDDA down to 2.5V, the PWM has issue like the screenshot below (Purple is for VDDA/VDDIO voltage, green is for PWM output) |
When the UVLO reset function disabled, when VDDA down to 2.8V, the PWM stop output, no glitch was found in the waveform. (Purple is for VDDA/VDDIO voltage, green is for PWM output) |
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2. Question
a. What's the I/O status when the DSP is reset? customer found the PWM is abnormal when the DSP is reset, does it happen in other customer?( The issue pulse is 5us)
b. When the DSP reset is enable(BOR), PWM stop output until the VDDA is down to 2.5V. When the BOR is disabled, the PWM output stop output when the VDDA is down to 2.8V. How to understand the result?
c. Is there any risks when the DSP just disable BOR? Does it affect other peripherals? Any application experience can share with customer?
3. Datasheet screenshot:
Best Regards
Songzhen Guo
