Part Number: TMS320F280049C-Q1
Other Parts Discussed in Thread: TMS320F280049C, TLIN1021DEVM, SYSCONFIG
Hi Champs,
Customer uses TI - LAUNCHXL -F280049C (TMS320F280049C)
For the particular series they are implementing the LIN/SCI Slave driver. While testing they are facing an issue
related to the receive data interrupt.
They are transmitting the LIN Header message (0x3D) from canoe but are unable to get the receive interrupt.
Please find the detailed pseudocode related to LIN Slave module initialization in the attachment.
This is how their setup is built:
Please find the details related to hardware connection mentioned below:
- We are using LIN transceiver(TLIN1021DEVM) to established the communication between the Evaluation board and
the LIN master(in our case we are using Canoe interface as LIN master).
- We have connected the LIN Transceiver Rx pin with launch pad Rx pin (i.e. PIN No.44) on Evaluation board and
LIN Transceiver Tx pin with Evaluation board( PIN NO.43).
- As per Evaluation Board user Guide, we are using BP so we have already made the switch S6 to BP selection and J101 jumper pins had been shorted.
With this connection, we tap the Rx pin (i.e. PIN 44) of the Evaluation board with the Logic analyzer. We were able to trace the Data Received on the Rx PIN.
Do you have any hints for us?
Thanks and regards,
Tamas
//*************************************************************************************************
//
// The following are defines for the LIN register offsets
//
//*************************************************************************************************
/* LIN module Base Address */
#define LINA_BASE 0x00006A00U
/* Global Control Register 0 */
#define LIN_REG_SCIGCR0 (*((volatile uint32_t *)(LINA_BASE + 0x0U)))
/* Global Control Register 1 */
#define LIN_REG_SCIGCR1 (*((volatile uint32_t *)(LINA_BASE + 0x4U)))
/* Global Control Register 2 */
#define LIN_REG_SCIGCR2 (*((volatile uint32_t *)(LINA_BASE + 0x8U)))
/* Interrupt Enable Register */
#define LIN_REG_SCISETINT (*((volatile uint32_t *)(LINA_BASE + 0xCU)))
/* Interrupt Disable Register */
#define LIN_REG_SCICLEARINT (*((volatile uint32_t *)(LINA_BASE + 0x10U)))
/* Set Interrupt Level Register */
#define LIN_REG_SCISETINTLVL (*((volatile uint32_t *)(LINA_BASE + 0x14U)))
/* Clear Interrupt Level Register */
#define LIN_REG_SCICLEARINTLVL (*((volatile uint32_t *)(LINA_BASE + 0x18U)))
/* Flag Register */
#define LIN_REG_SCIFLR (*((volatile uint32_t *)(LINA_BASE + 0x1CU)))
/* Interrupt Vector Offset Register 0 */
#define LIN_REG_SCIINTVECT0 (*((volatile uint32_t *)(LINA_BASE + 0x20U)))
/* Interrupt Vector Offset Register 1 */
#define LIN_REG_SCIINTVECT1 (*((volatile uint32_t *)(LINA_BASE + 0x24U )))
/* Length Control Register */
#define LIN_REG_SCIFORMAT (*((volatile uint32_t *)(LINA_BASE + 0x28U )))
/* Baud Rate Selection Register */
#define LIN_REG_BRSR (*((volatile uint32_t *)(LINA_BASE + 0x2CU )))
/* Emulation buffer Register */
#define LIN_REG_SCIED (*((volatile uint32_t *)(LINA_BASE + 0x30U)))
/* Receiver data buffer Register */
#define LIN_REG_SCIRD (*((volatile uint32_t *)(LINA_BASE + 0x34U)))
/* Transmit data buffer Register */
#define LIN_REG_SCITD (*((volatile uint32_t *)(LINA_BASE + 0x38U)))
/* Pin control Register 0 */
#define LIN_REG_SCIPIO0 (*((volatile uint32_t *)(LINA_BASE + 0x3CU)))
/* Pin control Register 2 */
#define LIN_REG_SCIPIO2 (*((volatile uint32_t *)(LINA_BASE + 0x44U)))
/* Compare register */
#define LIN_REG_COMP (*((volatile uint32_t *)(LINA_BASE + 0x60U )))
/* Receive data register 0 */
#define LIN_REG_RD0 (*((volatile uint32_t *)(LINA_BASE + 0x64U )))
/* Receive data register 1 */
#define LIN_REG_RD1 (*((volatile uint32_t *)(LINA_BASE + 0x68U )))
/* Acceptance mask register */
#define LIN_REG_MASK (*((volatile uint32_t *)(LINA_BASE + 0x6CU)))
/* LIN ID Register */
#define LIN_REG_ID (*((volatile uint32_t *)(LINA_BASE + 0x70U)))
/* Transmit Data Register 0 */
#define LIN_REG_TD0 (*((volatile uint32_t *)(LINA_BASE + 0x74U)))
/* Transmit Data Register 1 */
#define LIN_REG_TD1 (*((volatile uint32_t *)(LINA_BASE + 0x78U)))
/* Maximum Baud Rate Selection Register */
#define LIN_REG_MBRSR (*((volatile uint32_t *)(LINA_BASE + 0x7CU)))
/* IODFT for LIN */
#define LIN_REG_IODFTCTRL (*((volatile uint32_t *)(LINA_BASE + 0x90U)))
/* LIN Global Interrupt Enable Register */
#define LIN_REG_GLB_INT_EN (*((volatile uint32_t *)(LINA_BASE + 0xE0U)))
/* LIN Global Interrupt Flag Register */
#define LIN_REG_GLB_INT_FLG (*((volatile uint32_t *)(LINA_BASE + 0xE4U)))
/* LIN Global Interrupt Clear Register */
#define LIN_REG_GLB_INT_CLR (*((volatile uint32_t *)(LINA_BASE + 0xE8U)))
//*************************************************************************************************
//
// The following are defines for the bit fields Position in the SCIFLR register
//
//*************************************************************************************************
#define LIN_SCIFLR_BRKDT_POS 0U // Break-detect Flag (SCI compatible mode)
#define LIN_SCIFLR_WAKEUP_POS 1U // Wake-up Flag
#define LIN_SCIFLR_IDLE_POS 2U // SCI receiver in idle state (SCI compatible mode)
#define LIN_SCIFLR_BUSY_POS 3U // Busy Flag
#define LIN_SCIFLR_TIMEOUT_POS 4U // LIN Bus IDLE timeout Flag (LIN only)
#define LIN_SCIFLR_TOAWUS_POS 6U // Timeout After Wakeup Signal Flag (LIN only)
#define LIN_SCIFLR_TOA3WUS_POS 7U // Timeout After 3 Wakeup Signals Flag (LIN only)
#define LIN_SCIFLR_TXRDY_POS 8U // Transmitter Buffer Ready Flag
#define LIN_SCIFLR_RXRDY_POS 9U // Receiver Buffer Ready Flag
#define LIN_SCIFLR_TXWAKE_POS 10U // SCI Transmitter Wakeup Method Select
#define LIN_SCIFLR_TXEMPTY_POS 11U // Transmitter Empty Flag
#define LIN_SCIFLR_RXWAKE_POS 12U // Receiver Wakeup Detect Flag
#define LIN_SCIFLR_IDTXFLAG_POS 13U // Identifier On Transmit Flag (LIN only)
#define LIN_SCIFLR_IDRXFLAG_POS 14U // Identifier on Receive Flag
#define LIN_SCIFLR_PE_POS 24U // Parity Error Flag
#define LIN_SCIFLR_OE_POS 25U // Overrun Error Flag
#define LIN_SCIFLR_FE_POS 26U // Framing Error Flag
#define LIN_SCIFLR_NRE_POS 27U // No-Response Error Flag (LIN only)
#define LIN_SCIFLR_ISFE_POS 28U // Inconsistent Sync Field Error Flag (LIN only)
#define LIN_SCIFLR_CE_POS 29U // Checksum Error Flag (LIN only)
#define LIN_SCIFLR_PBE_POS 30U // Physical Bus Error Flag (LIN only)
#define LIN_SCIFLR_BE_POS 31U // Bit Error Flag (LIN only)
//*************************************************************************************************
/*LIN Slave Drive Initialization Api Description*/
//
//*************************************************************************************************
void LINDrv_Init(void)
{
/* Initialize LIN state to IDLE. */
g_LIN_State = LIN_STATE_IDLE;
EALLOW;
/* LIN Tx GPIO Configuration */
GPIO_setPinConfig(GPIO_28_LINA_TX);
/**/
GPIO_setPadConfig(28,GPIO_PIN_TYPE_STD);
GPIO_setDirectionMode(28,GPIO_DIR_MODE_OUT);
GPIO_setQualificationMode(GPIO_28_LINA_TX, GPIO_QUAL_ASYNC);
/* LIN Rx GPIO Configuration */
GPIO_setPinConfig(GPIO_29_LINA_RX);
GPIO_setPadConfig(29,GPIO_PIN_TYPE_STD);
GPIO_setDirectionMode(29,GPIO_DIR_MODE_IN);
GPIO_setQualificationMode(GPIO_29_LINA_RX, GPIO_QUAL_ASYNC);
/* Reset the Module */
LIN_REG_SCIGCR0 |= LIN_SCIGCR0_RESET;
/* Reset the Software Reset Bit */
LIN_REG_SCIGCR1 &= ~(LIN_SCIGCR1_SWNRST);
/* Configure the LINRx and LINTx Pin */
LIN_REG_SCIPIO0 |= (LIN_SCIPIO0_RXFUNC | LIN_SCIPIO0_TXFUNC);
/* Select SCI Mode */
// LIN_REG_SCIGCR1 |= LIN_REG_SCIGCR1 & (~LIN_SCIGCR1_LINMODE);
LIN_REG_SCIGCR1 |= LIN_SCIGCR1_LINMODE;
/* Configure the LIN Module in Slave mode */
LIN_REG_SCIGCR1 |= LIN_SCIGCR1_CLK_MASTER;
/* Disable the ID4/ID5 bits for length control*/
LIN_REG_SCIGCR1 |= (LIN_SCIGCR1_TIMINGMODE);
/* Debug mode */
LIN_REG_SCIGCR1 |= (LIN_REG_SCIGCR1 & ~(LIN_SCIGCR1_CONT));
/* Configure the Parity */
LIN_REG_SCIGCR1 |= (LIN_REG_SCIGCR1 & ~(LIN_SCIGCR1_PARITYENA));
/* Configure the SCI Stop Bits */
LIN_setSCIStopBits(LINA_BASE,LIN_SCI_STOP_ONE);
/*Set character length as 8-bits*/
LIN_setSCICharLength(LINA_BASE, CHAR_LENGTH);
/* Frame Length */
LIN_setSCIFrameLength(LINA_BASE, FRAME_LENGTH);
/* Select Multi-buffer */
LIN_REG_SCIGCR1 |= (LIN_REG_SCIGCR1 & ~(LIN_SCIGCR1_MBUFMODE));
/* Disable LOOP-BACK Mode */
LIN_REG_SCIGCR1 |= (LIN_REG_SCIGCR1 &~(LIN_SCIGCR1_LOOPBACK));
//LIN_REG_SCIGCR1 |= LIN_SCIGCR1_LOOPBACK;
/* Synch break and synch delimiter additional bits */
// LIN_REG_COMP |= (LIN_SYNCH_BREAK_LEN | ((LIN_SYNCH_DELIMITER_LEN - LIN_CONST_NO_ONE) << LIN_COMP_SDEL_S));
/* Configure the BaudRate */
LINDrv_SetBuadRate(LIN_CONFIG_BAUDRATE);
/* Configure the Slave ID for message filtering */
LIN_REG_SCIGCR1 |= (LIN_REG_SCIGCR1 & ~(LIN_SCIGCR1_HGENCTRL));
/* Configure the Filter Compare ID */
//LIN_REG_ID |= ((uint32_t)LIN_MESSAGEID_COMPARE_CONFIG << LIN_CONST_NO_EIGHT);
/* Configure the Filter Mask */
LIN_REG_MASK |= ((uint32_t)LIN_RXMESSAGEID_FILTERMASK << LIN_CONST_NO_SIXTEEN);
/* Enable the Transmit */
LIN_REG_SCIGCR1 |= LIN_SCIGCR1_TXENA;
/* Enable the Receive */
LIN_REG_SCIGCR1 |= LIN_SCIGCR1_RXENA;
/* Enable Interrupt - Break Detection Interrupt,Wakeup Interrupt,
Timeout Interrupt,Tx INterrupt , RX interrupt ,
ID Interrupt , Parity Error Intrrupt,
Sync Frame Error Interrupt, Checksum Error Interrupt,
Bit Error Interrupt*/
LIN_REG_SCISETINT |= (LIN_SCISETINT_SETBRKDTINT | LIN_SCISETINT_SETWAKEUPINT |
LIN_SCISETINT_SETTIMEOUTINT | LIN_SCISETINT_SETTXINT |
LIN_SCISETINT_SETRXINT | LIN_SCISETINT_SETIDINT |
LIN_SCISETINT_SETPEINT | LIN_SCISETINT_SETISFEINT |
LIN_SCISETINT_SETCEINT | LIN_SCISETINT_SETBEINT);
/* Set the Interrupt Handler */
Interrupt_register(INT_LINA_0, &LINDrv_IntLevel0Handle);
/* Enable Global Interrupt */
LIN_REG_GLB_INT_EN |= LIN_GLB_INT_EN_GLBINT0_EN;
/* Clear the Global Interrupt Status */
LIN_REG_GLB_INT_FLG |= LIN_GLB_INT_CLR_INT0_FLG_CLR;
/* Reset the Software Reset Bit */
LIN_REG_SCIGCR1 |= (LIN_SCIGCR1_SWNRST);
EDIS;
/* Enable Interrupts */
Interrupt_enable(INT_LINA_0);
}
