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TMS320F280039C: How to calculate deadband value with dead time of gate driver?

Part Number: TMS320F280039C
Other Parts Discussed in Thread: UCC21530-Q1

Hi Team, 

I need to understand how deadtime is calculated.

I found deadtime value in hal.h of tidm_02012 example as follows.

#define MTR1_PWM_DBFED_CNT      86

#define MTR1_PWM_DBRED_CNT      86

This reference uses the UCC21530-Q1 that supports programmable dead time. 

And by referring to the schematic, the dead time can be estimated to be 30ns.

Now, I wonder why the MTR1_PWM_DBFED_CNT is set to 86 .

When the MTR1_PWM_DBFED_CNT is 86, delay count is calculated in 717ns at 120Mz.

The DT of gate driver is 30ns, but the C2000's PWM delay count are set to 717ns.


How do I calculate the DC value of the PWM by referring to the DT of the gate driver?

  • I think the source code snippet in the reference design is misleading. It says "system clocks" but that is not usually the case. The dead-bands are function of TBLCLK which may not be the same as SYSCLK.

    You need to first calculate EPWMCLK then TBCLK then see page 2196 of the TRM and especially  "Table 20-11. Dead-Band Delay Values in μS as a Function of DBFED and DBRED"

  • Hi, 

    I checked the clock settings in the source code.

    Both system clock and TBCLK are 120MHz.

    I got 717ns by calculating as below.

    MTR1_PWM_DBFED_CNT * 1/120MHz = 86 * 8.333333ns

  • Hello SY Yoon,

    The deadtime programmed in the F280039C device's EPWM module and UCC21530-Q1 are independent. Your timing calculations are correct and the PWM outputs will have a deadband equal to the larger of the two values. So, in this case, the actual PWM output's deadband should be ~717ns.

    To better understand this, please refer to "Condition C" of Section 8.4.2.2 of UCC21530-Q1's datasheet. Since, the INA, INB signals coming from the F280039 will already have a 717ns deadband which is > 30ns programmed in the UCC21530-Q1, it will not introduce any additional deadband.

    Hope this helps.

    Thank you.