• State TI Thinks Resolved
  • Locked Locked
  • Replies 7 replies
  • Answers 1 answer
  • Subscribers 83 subscribers
  • Views 534 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS320F28379D: how to attain ADC maximum samples given as 4.4 MSPS

vikas rastogi
Intellectual 295 points
Part Number: TMS320F28379D

Hi TI-Team,

We're using differential ADC in our project. We're in doubt with the ADC conversion timing and Acquisition period.
In datasheet it was mentioned that for 16-bit ADC the minimum acquisition window should be 320nS, is that should be fixed or we can vary it.
Firstly how to decide which acquisition window should I use. Our's is a low impedance input for the ADC(buffer). Can we go below 320nS was that make any problem in ADC values.

In datasheet it was mentioned that 1.1MSPS each and upto 4.4MSPS throughput of system. Was that mean throughput of Single adc, is it so how to attain 4.4 MSPS

  • 0
    TI__Intellectual 1050 points

    Hi Vikas,

    Kindly refer the section 11.15.2 Choosing an Acquisition Window Duration from TMS320F2837xD_Technical Reference Manual to decide the correct ACQPS. 

    In 16-bit mode, the minimum sample and hold time for the ADC is 320ns. Sample and hold time is (ACQPS+1)*SYSCLK period.  If SYSCLK is set at 200Mhz, ACQPS value to meet the minimum sample and hold time is 63 [(320ns/(1/200MHz)) - 1]. See description of registers ADCSOCxCTL (ACQPS) for more details. Note that the sample and hold time is not a function by ADCCLK, but by ACQPS setting and SYSCLK. 

    Also note that maximum throughput in 16-bit mode (with the 320ns minimum sample and hold time) is at 1.1MSPS.  You will get inaccurate conversion results if sample and hold time is less than this value. You can interleave conversions on the different ADC modules if you want to attain higher throughput overall (up to 4.4 MSPS).

    Regards,

    Meghavi

  • 0 in reply to Meghavi Tank
    Intellectual 295 points

    Hi ,

        We calculated the conversion time for prescale 0,

        Aquisition time 320 + 32*5 = 480 ns  // 32   latching time

    According this calculation the throughput will be more than 2MSPS so how you are saying maximum we can attain 1.1 MSPS.

    Kindly explain.

  • 0 in reply to vikas rastogi
    TI__Intellectual 1050 points

    Hi Vikas,

    I am not able to understand the above calculation.

    But, the total conversion time as mentioned in the datasheet is 915ns. So, the maximum throughput we can attain is: 1/915ns = 1.092 MSPS. I hope this clears your confusion.

    Regards,

    Meghavi

  • 0 in reply to Meghavi Tank
    Intellectual 295 points

    Dear Meghavi,

    Yes, in datasheet the conversion time is 915 ns but we will be happy to know the breakup of this calculation.

    Refer to Fig. 11-15 and Table 11-13 of Technical Reference Manual. Total time for one sample is tSH + tEOC = 320 ns + 31*5ns (for PRESCALE 0) = 475 nS. This value is less than 915 nS suggested in datasheet. We also measured ADC ISR frequency by GPIO toggle and found this time to be 490 nS.

    Can you please suggest?

    Regards,
    Jitendra

  • 0 in reply to vikas rastogi
    Intellectual 295 points

    Hi Meghavi,

    Gentle reminder. As we need differential channels for high speed and high performance measurement, it is important for us to understand this in detail otherwise we will mess up the control loop.

  • 0 in reply to vikas rastogi
    TI__Intellectual 1050 points

    Hi Jitendra,

    Apologies for the delay in response. Maximum ADCCLK should be set to 50MHz for 16-bit resolution (as mentioned in the section 8.10.1.2.1). Based on that, the overall conversion time would be tSH + tEOC = 320 ns + 31*20ns (for 50MHz) = 940 nS. 

    Regards,

    Meghavi