TMS320F28388D: http Client request using the F28388D

Jonathan,

There is a Readme file in the example folder which mentions the steps to run this example. 

It works only on CM core, however C28x should configure the pinmux configuration.  This can be done by running the ethernet_c28x_config project located in the folder <C2000Ware>\driverlib\f2838x\examples\cm\ethernet\CCS. 

Best Regards

Siddharth

Hi Siddarth,

Thank you for your support. Here is the customer's response below.

Do I have to mix the 2 programs?

cm_common_config_c28x.c
from the project ethernet_c28x_config

or just run/debug the config, then run/debug the enet_lwip

I did that, and nothing, I can't ping 192.168.0.4

C28xx_CPU1: GEL Output:
Memory Map Initialization Complete
C28xx_CPU1: GEL Output:
... DCSM Initialization Start ...
C28xx_CPU1: GEL Output:
... DCSM Initialization Done ...
C28xx_CPU1: GEL Output:
 CPU2 is out of reset and configured to wait boot.
 (If you connected previously, may have to resume CPU2 to reach wait boot loop.)
C28xx_CPU1: GEL Output:
 CM is out of reset and configured to wait boot.
 (If you connected previously, may have to resume CM to reach wait boot loop.)
C28xx_CPU1: GEL Output:
... DCSM Initialization Start ...
C28xx_CPU1: GEL Output:
... DCSM Initialization Done ...
C28xx_CPU1: GEL Output:
 CPU2 is out of reset and configured to wait boot.
 (If you connected previously, may have to resume CPU2 to reach wait boot loop.)
C28xx_CPU1: GEL Output:
 CM is out of reset and configured to wait boot.
 (If you connected previously, may have to resume CM to reach wait boot loop.)
C28xx_CPU1: If erase/program (E/P) operation is being done on one core, the other core should not execute from shared-RAM (SR) as they are used for the E/P code. User code execution from SR could commence after both flash banks are programmed.
C28xx_CPU1: Only CPU1 on-chip Flash Plugin can configure clock for CPU1, CPU2 and CM Flash operations. Plugin automatically configures PLL when CPU1 Flash operations are invoked. However, if users want to do only CPU2 or CM Flash operations without doing a prior CPU1 operation in the current session, they should click on 'Configure Clock' button in CPU1's on-chip Flash Plugin before invoking CPU2 and CM Flash operations. When this button is used, Flash Plugin will configure the clock for CPU1/CPU2 at 190MHz and CM at 95MHz using INTOSC2 as the clock source. Plugin will leave PLL config like this and user application should configure the PLL as required by application.
C28xx_CPU1: GEL Output:
... DCSM Initialization Start ...
C28xx_CPU1: GEL Output:
... DCSM Initialization Done ...
C28xx_CPU1: GEL Output:
 CPU2 is out of reset and configured to wait boot.
 (If you connected previously, may have to resume CPU2 to reach wait boot loop.)
C28xx_CPU1: GEL Output:
 CM is out of reset and configured to wait boot.
 (If you connected previously, may have to resume CM to reach wait boot loop.)




    //
    // Initialize device clock and peripherals
    //
    Device_init();

    //
    // Boot CM core
    //
#ifdef _FLASH
    Device_bootCM(BOOTMODE_BOOT_TO_FLASH_SECTOR0);
#else
    Device_bootCM(BOOTMODE_BOOT_TO_S0RAM);
#endif

    //
    // Disable pin locks and enable internal pull-ups.
    //
    Device_initGPIO();

#ifdef ETHERNET
    //
    // Set up EnetCLK to use SYSPLL as the clock source and set the
    // clock divider to 2.
    //
    // This way we ensure that the PTP clock is 100 MHz. Note that this value
    // is not automatically/dynamically known to the CM core and hence it needs
    // to be made available to the CM side code beforehand.
    SysCtl_setEnetClk(SYSCTL_ENETCLKOUT_DIV_2, SYSCTL_SOURCE_SYSPLL);

    //
    // Configure the GPIOs for ETHERNET.
    //

    //
    // MDIO Signals
    //
    GPIO_setPinConfig(GPIO_105_ENET_MDIO_CLK);
    GPIO_setPinConfig(GPIO_106_ENET_MDIO_DATA);

    //
    // Use this only for RMII Mode
    //GPIO_setPinConfig(GPIO_73_ENET_RMII_CLK);
    //

    //
    //MII Signals
    //
    GPIO_setPinConfig(GPIO_109_ENET_MII_CRS);
    GPIO_setPinConfig(GPIO_110_ENET_MII_COL);

    GPIO_setPinConfig(GPIO_75_ENET_MII_TX_DATA0);
    GPIO_setPinConfig(GPIO_122_ENET_MII_TX_DATA1);
    GPIO_setPinConfig(GPIO_123_ENET_MII_TX_DATA2);
    GPIO_setPinConfig(GPIO_124_ENET_MII_TX_DATA3);

    //
    //Use this only if the TX Error pin has to be connected
    //GPIO_setPinConfig(GPIO_46_ENET_MII_TX_ERR);
    //

    GPIO_setPinConfig(GPIO_118_ENET_MII_TX_EN);

    GPIO_setPinConfig(GPIO_114_ENET_MII_RX_DATA0);
    GPIO_setPinConfig(GPIO_115_ENET_MII_RX_DATA1);
    GPIO_setPinConfig(GPIO_116_ENET_MII_RX_DATA2);
    GPIO_setPinConfig(GPIO_117_ENET_MII_RX_DATA3);
    GPIO_setPinConfig(GPIO_113_ENET_MII_RX_ERR);
    GPIO_setPinConfig(GPIO_112_ENET_MII_RX_DV);

    GPIO_setPinConfig(GPIO_44_ENET_MII_TX_CLK);
    GPIO_setPinConfig(GPIO_111_ENET_MII_RX_CLK);

    //
    //Power down pin to bring the external PHY out of Power down
    //
    GPIO_setDirectionMode(108, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(108, GPIO_PIN_TYPE_PULLUP);
    GPIO_writePin(108,1);

    //
    //PHY Reset Pin to be driven High to bring external PHY out of Reset
    //

    GPIO_setDirectionMode(119, GPIO_DIR_MODE_OUT);
    GPIO_setPadConfig(119, GPIO_PIN_TYPE_PULLUP);
    GPIO_writePin(119,1);
#endif



C28xx_CPU1: GEL Output:
Memory Map Initialization Complete
C28xx_CPU1: GEL Output:
... DCSM Initialization Start ...
C28xx_CPU1: GEL Output:
... DCSM Initialization Done ...
C28xx_CPU1: GEL Output:
 CPU2 is out of reset and configured to wait boot.
 (If you connected previously, may have to resume CPU2 to reach wait boot loop.)
C28xx_CPU1: GEL Output:
 CM is out of reset and configured to wait boot.
 (If you connected previously, may have to resume CM to reach wait boot loop.)
C28xx_CPU1: GEL Output:
... DCSM Initialization Start ...
C28xx_CPU1: GEL Output:
... DCSM Initialization Done ...
C28xx_CPU1: GEL Output:
 CPU2 is out of reset and configured to wait boot.
 (If you connected previously, may have to resume CPU2 to reach wait boot loop.)
C28xx_CPU1: GEL Output:
 CM is out of reset and configured to wait boot.
 (If you connected previously, may have to resume CM to reach wait boot loop.)
C28xx_CPU1: If erase/program (E/P) operation is being done on one core, the other core should not execute from shared-RAM (SR) as they are used for the E/P code. User code execution from SR could commence after both flash banks are programmed.
C28xx_CPU1: Only CPU1 on-chip Flash Plugin can configure clock for CPU1, CPU2 and CM Flash operations. Plugin automatically configures PLL when CPU1 Flash operations are invoked. However, if users want to do only CPU2 or CM Flash operations without doing a prior CPU1 operation in the current session, they should click on 'Configure Clock' button in CPU1's on-chip Flash Plugin before invoking CPU2 and CM Flash operations. When this button is used, Flash Plugin will configure the clock for CPU1/CPU2 at 190MHz and CM at 95MHz using INTOSC2 as the clock source. Plugin will leave PLL config like this and user application should configure the PLL as required by application.
Cortex_M4_0: GEL Output: Memory Map Initialization Complete
Cortex_M4_0: GEL Output: Windowed Watchdog Enabled
Cortex_M4_0: GEL Output: UART0 Enabled
Cortex_M4_0: Only CPU1 on-chip Flash Plugin can configure clock for CPU1, CPU2 and CM Flash operations. Plugin automatically configures PLL when CPU1 Flash operations are invoked. However, if users want to do only CPU2 or CM Flash operations without doing a prior CPU1 operation in the current session, they should click on 'Configure Clock' button in CPU1's on-chip Flash Plugin before invoking CPU2 and CM Flash operations. When this button is used, Flash Plugin will configure the clock for CPU1/CPU2 at 190MHz and CM at 95MHz using INTOSC2 as the clock source. Plugin will leave PLL config like this and user application should configure the PLL as required by application.

Best regards,

Jonathan

Jonathan,

You can use cm_common_config_c28x with "ETHERNET" as a predefined symbol . 

You will have to load the ,out from this project on c28x and then run it.

You can then load the enet_lwip .out file on the ARM core and run it. 

Let me know if you are able to run it. 

Best Regards

Siddharth

Hi Siddharth

(I can now post directly)

I already did that

I open the cm_common_config_c28x project and debug / Run the project
then I open the enet_lwip project and debug / Run the project

I plug the ethernet cable from F28388D ethernet port into my laptop, put a static IP 192.168.0.3 on it
try ping 192.168.0.4
No answer

Is there a simpler example to run just to make http GET or POST
get the results and send them to CPU1 and to COM port over USB

I don't need a server on F28388D
Thanks

Best regards
Lotfi

Hi Lotfi,

The enet_lwip project has to be loaded on the CM core . You can debug the CM core to check if the code has executed successfully. 

You can halt the execution and share the screenshot to debug this further.

Best Regards

Siddharth

Hi

I downloaded C2000Ware V4.03 instead of 3.04  but the results are the same

Here is the capture when running the enet_lwip on the CM

I am not sure I am doing the right things:

First I debug/run the project

 cm_common_config_c28x

then I make the enet_lwip  project active and I debug it

I create another debug config since the target change

So far, I have no ping on 192.168.0.4

thanks

Hi, 

After building the project, pls launch the debug session by following the below steps

1. Click on "View->TargetConfigurations" , select the project and the corresponding target configuration file. Right click on it and click on "Launch selected configuration"

2. When the debug session is launched , you can select the cores and connect to the cores

 First connect to "C28xx_CPU1" core and then connect to "Cortex_M4_0" core.

3. Select the "C28xx_CPU1:" core and then click on "Run->Load->Load Program" , Specify the .out file generated from cm_common_config_c28x project and load it and then run it

4. Select the "Cortex_M4_0" core , then click on "Run->Load->Load Program", specify the .out file generated from enet_lwip project , load it and then run it.

Now both the cores are loaded and the program is running. You should be able to get the response to the ping now.

Best Regards

Siddharth

It finally works! Thanks

Do you have a simple example to Is there a simpler example to run just to make http GET or POST
get the results and send them to CPU1 and to COM port over USB

and how to transfer variables data from CPU1 to CM and vice versa?

Thanks

Hi, 

Glad that you got it working. 

This is the only example that is currently available .  

There is another example located at<C2000Ware>\driverlib\f2838x\examples\c28x_cm\ethernet which prepares the Ethernet frame to be sent to the CM core
using IPC Message RAM.  This doesn't using any TCP/IP stack and only uses the Ethernet drivers.

Best Regards

Siddharth