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LAUNCHXL-F280049C: Problem SPI communication between 2 boards

Part Number: LAUNCHXL-F280049C
Other Parts Discussed in Thread: SYSCONFIG, C2000WARE

Hello,

I am studying how this micronctroller works and I am having problems understanding how to properly set a communication between two LAUNCHXL-F280049C via SPI

I would like to transfer an array of 11 elements of uint16_t type using the FIFO interrupts from the master to the slave. My configuration and code are the following (I am using sysconfig).

 Board 1 TX ISR(master): 

__interrupt void spiTxFIFOISR(){

    for(i=0; i< dim; i++){
        SPI_writeDataNonBlocking(mySPI0_BASE, data[i]);
    }

    counter++;

    SPI_clearInterruptStatus(mySPI0_BASE, SPI_INT_TXFF);
    Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP6);
}

Board 1 sysconfig: 

 Board 2 RX ISR(slave):

__interrupt void spiRxFIFOISR(){

    for (i = 0; i< dim; i++){
        data[i] = SPI_readDataNonBlocking(mySPI0_BASE);
    }

    counter++;

    SPI_clearInterruptStatus(mySPI0_BASE, SPI_INT_RXFF);
    Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP6);
}

Board 2 sysconfig: 

(Note that I have enabled and remapped both the interrupts in the setup part of the main which is not present in the shown codes)

I expect to receive correctly the array of data I am sending on the slave but what I see is the same array shambled at each iteration of the receive interrupt. Could you explain me what I am doing wrong? I am following the example provided by TI for the SPI communication but I don't get where are my mistakes.

On the left there's the array I am sending while on the right there's the array I receive.

Thank you in advance Slight smile.

Best regards,

Edoardo

  • Hi Edoardo,

    Have you tried the C2000ware example? There is one example that uses 2 SPI instances from a single launchpad. Could you please try this to ensure there are no issues in TX and RX?

    Regarding your setup with 2 launchpads, please ensure the SPI pins are connected correctly, both have common ground, etc.

    Regards,

    Veena

  • Dear Veena, 


    Thank you for your reply.

    I have tried the ex4 for the SPI from C2000ware examples and I have found out that the problem I had was on the sysconfig side. I was setting wrongly the FIFO interrupt levels because I previously set for the receiver and transmitter the same level (11/16 since I was transmitting a 16-elements array). By configuring the transmitter FIFO level to 5/16 and the receiver FIFO level to 11/16 I am receiving the data correctly, without it being shambled.

    But I don't really understand why. I tought that interrupts would trigger when the related FIFO contained a number of elements equal to the one defined by the level. For example, if the TX FIFO Interrupt level is 11/16, the interrupt would have been called when in the TX FIFO there where 11 elements and, following the same idea, if the RX FIFO Interrupt level is 11/16, the interrupt would have been triggered when the RX FIFO has 11 elements inside.

    Could you tell me where I am misunderstanding this concept? 

    Thank you in advance Slight smile

    Best Regards, 

    Edoardo

  • On the TX FIFO side, TXFFIL= 11, you will get an interrupt when there are 11 or fewer number of words left in the buffer. For example, if you had filled in the buffer full (16 words), the interrupt is triggered after sending 5 words. After 5 words, TX FIFO will contain 11 words and this triggers the interrupt.

    Regards,

    Veena

  • Dear Veena, 

    Thank you for your response. Now it is all clear and I understand how it should work.

    Kind Regards, 

    Edoardo