TMS320F28375D: about hrpwm operation

naoki takahashi

Hi team,

I am using HRPWM with TMS320F28375D.

PWM is generated by setting CMPA/CMPB using up/down counters.
We have manufactured many identical boards, but only one of them has the following phenomenon.
What are the possible causes?
(Occurs once a day. Does not occur if HRPWM is not used)

・PWM of about 20ns is output even though CMPA/CMPB is not controlled.
・Even though the TRIP signal is input and the gate driver is turned off, PWM of about 20ns is output.

CH1:ePWM5(Hi SIDE)

CH2:ePWM5(Lo SIDE)

CH3:ePWM6(Hi SIDE)

CH4:ePWM6(Lo SIDE)

CH5:ePWM8(Hi SIDE)

CH6:ePWM8(Lo SIDE)

CH7:NOT USE

CH8:TRIP SIGNAL

Best regards,
Takahashi

over 3 years ago

0 Ryan Ma over 3 years ago

TI__Mastermind 27736 points

Hi Takahashi-san,

What is your expected output when the trip signal occurs on CH1-6? Are you referring to the jitters that are occurring at the output when the trip is asserted? (The dotted lines in below screenshot)

Could you send me the working waveform when HRPWM is not enabled?

Thank you,

Ryan Ma

0 naoki takahashi over 3 years ago in reply to Ryan Ma

Prodigy 40 points

Yes.I am referring to the jitter when the trip signal is asserted. (The dotted lines in screenshot)
Jitter is occurring even though the trip signal is asserted and not in control.
After the trip signal is asserted, I expect ch1-6 to be at a constant Hi level.

I send the working waveform, when HRPWM is not enabled.

0 Ryan Ma over 3 years ago in reply to naoki takahashi

TI__Mastermind 27736 points

Hi Naoki-san,

Are you synchronizing these PWMs by any chance? If so, you should not syncrhonize every PWM period, and only sync when needed otherwise there will be jitter as you see in your waveform.

Best,

Ryan Ma

0 naoki takahashi over 3 years ago in reply to Ryan Ma

Prodigy 40 points

Are you referring to the NOTE in SPRUHM8I?
We set TBCTL[SYNCOSEL] to 0.
As a new finding, the same phenomenon occurs when FFh is set in the HRMSTEP Register.
(It's an experimental setting, usually using SFO())

We expect the HRMSTEP register to be written with an abnormal value, causing jitter. (dotted line in screenshot)
What are the possible causes?

0 Ryan Ma over 3 years ago in reply to naoki takahashi

TI__Mastermind 27736 points

Yes, that is the note I am referring to.

Did setting TBCTL[SYNCOSEL] solve the issue?

Are you now only seeing the same phenomenon when FFh is set in HRMSTEP register?

Could you share your code in how you're configuring HRPWM with just the basic needed to replicate your findings?

0 naoki takahashi over 3 years ago in reply to Ryan Ma

Prodigy 40 points

I have set TBCTL[SYNCOSEL] but the issue is not resolved.

The same phenomenon occurs when the HRMSTEP register is set to approximately 7Ch-FFh.

Shares the HRPWM register settings.

Fullscreen EPWM_Setting.c Download


#define SELECT_HRPWM		1	// Disable(0):Enable(1)


//===================================================================
/* EPWM defines */
#define PWM1_PERIOD				5264			// 5264 cycles ->  9.5kHz @PWMCLK(100MHz)=SYSCLK(200MHz)/2
#define PWM2_PERIOD				5264			// 5264 cycles ->  9.5kHz @PWMCLK(100MHz)=SYSCLK(200MHz)/2
#define PWM3_PERIOD				5264			// 5264 cycles ->  9.5kHz @PWMCLK(100MHz)=SYSCLK(200MHz)/2
#define PWM4_PERIOD				5264			// 5264 cycles ->  9.5kHz @PWMCLK(100MHz)=SYSCLK(200MHz)/2
#define PWM5_PERIOD				1316			// 1316 cycles -> 38.0kHz @PWMCLK(100MHz)=SYSCLK(200MHz)/2
#define PWM6_PERIOD				1316			// 1316 cycles -> 38.0kHz @PWMCLK(100MHz)=SYSCLK(200MHz)/2
#define PWM7_PERIOD				1316			// 1316 cycles -> 38.0kHz @PWMCLK(100MHz)=SYSCLK(200MHz)/2
#define PWM8_PERIOD				1316			// 1316 cycles -> 38.0kHz @PWMCLK(100MHz)=SYSCLK(200MHz)/2
#define PWM9_PERIOD				1316			// 1316 cycles -> 38.0kHz @PWMCLK(100MHz)=SYSCLK(200MHz)/2
#define PWM10_PERIOD			1316			// 1316 cycles -> 38.0kHz @PWMCLK(100MHz)=SYSCLK(200MHz)/2
#define PWM11_PERIOD			876				//  876 cycles -> 57.0kHz @PWMCLK(100MHz)=SYSCLK(200MHz)/2

#define EPWM1REGS_TBPHS			(0x0000)		// Phase   0deg [   0 counts]
#define EPWM2REGS_TBPHS			(0x0000)		// Phase   0deg [   0 counts]
#define EPWM3REGS_TBPHS			(0x0000)		// Phase   0deg [   0 counts]
#define EPWM4REGS_TBPHS			(0x0000)		// Phase   0deg [   0 counts]
#define EPWM5REGS_TBPHS			(0x0000)		// Phase   0deg [   0 counts]
#define EPWM6REGS_TBPHS			(0x0524)		// Phase 180deg [1316 counts]
#define EPWM7REGS_TBPHS			(0x0292)		// Phase  90deg [ 658 counts]
#define EPWM8REGS_TBPHS			(0x0292)		// Phase 270deg [ 658 counts]
#define EPWM9REGS_TBPHS			(0x0000)		// Phase   0deg [   0 counts]
#define EPWM10REGS_TBPHS		(0x0524)		// Phase 180deg [1316 counts]
#define EPWM11REGS_TBPHS		(0x0000)		// Phase   0deg [   0 counts]


void EPWM_initEpwm(void)
{
	EALLOW;
	/*** Trip PWM ***/
	EPwm1Regs.TZFRC.bit.OST  = 1;
	EPwm2Regs.TZFRC.bit.OST  = 1;
	EPwm3Regs.TZFRC.bit.OST  = 1;
	EPwm4Regs.TZFRC.bit.OST  = 1;
	EPwm5Regs.TZFRC.bit.OST  = 1;
	EPwm6Regs.TZFRC.bit.OST  = 1;
	EPwm7Regs.TZFRC.bit.OST  = 1;
	EPwm8Regs.TZFRC.bit.OST  = 1;
	EPwm9Regs.TZFRC.bit.OST  = 1;
	EPwm10Regs.TZFRC.bit.OST = 1;
	EPwm11Regs.TZFRC.bit.OST = 1;

	/*** Stop PWM Timer ***/
	CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0;		// Turn off the EPWM clock

	/*** Setup TBPRD ***/
	// Set period to counts
	EPwm1Regs.TBPRD  = PWM1_PERIOD;
	EPwm2Regs.TBPRD  = PWM2_PERIOD;
	EPwm3Regs.TBPRD  = PWM3_PERIOD;
	EPwm4Regs.TBPRD  = PWM4_PERIOD;
	EPwm5Regs.TBPRD  = PWM5_PERIOD;
	EPwm6Regs.TBPRD  = PWM6_PERIOD;
	EPwm7Regs.TBPRD  = PWM7_PERIOD;
	EPwm8Regs.TBPRD  = PWM8_PERIOD;
	EPwm9Regs.TBPRD  = PWM9_PERIOD;
	EPwm10Regs.TBPRD = PWM10_PERIOD;
	EPwm11Regs.TBPRD = PWM11_PERIOD;

	/***
	 * Set phase
	 *  Other then the standard, it is delayed by 2 clocks.
	 *  Therefore, two clocks ahead are set.
	 *  NOTE: TBPHSHR must not be used.
	 ***/
	EPwm1Regs.TBPHS.bit.TBPHS  = EPWM1REGS_TBPHS;
	EPwm2Regs.TBPHS.bit.TBPHS  = EPWM2REGS_TBPHS;
	EPwm3Regs.TBPHS.bit.TBPHS  = EPWM3REGS_TBPHS;
	EPwm4Regs.TBPHS.bit.TBPHS  = EPWM4REGS_TBPHS;
	EPwm5Regs.TBPHS.bit.TBPHS  = EPWM5REGS_TBPHS;
	EPwm6Regs.TBPHS.bit.TBPHS  = EPWM6REGS_TBPHS;
	EPwm7Regs.TBPHS.bit.TBPHS  = EPWM7REGS_TBPHS;
	EPwm8Regs.TBPHS.bit.TBPHS  = EPWM8REGS_TBPHS;
	EPwm9Regs.TBPHS.bit.TBPHS  = EPWM9REGS_TBPHS;
	EPwm10Regs.TBPHS.bit.TBPHS = EPWM10REGS_TBPHS;
	EPwm11Regs.TBPHS.bit.TBPHS = EPWM11REGS_TBPHS;

	/*** Clear counter ***/
	EPwm1Regs.TBCTR  = 0;
	EPwm2Regs.TBCTR  = 0;
	EPwm3Regs.TBCTR  = 0;
	EPwm4Regs.TBCTR  = 0;
	EPwm5Regs.TBCTR  = 0;
	EPwm6Regs.TBCTR  = 0;
	EPwm7Regs.TBCTR  = 0;
	EPwm8Regs.TBCTR  = 0;
	EPwm9Regs.TBCTR  = 0;
	EPwm10Regs.TBCTR = 0;
	EPwm11Regs.TBCTR = 0;

	/*** Set Compare A values ***/
	EPwm1Regs.CMPA.all  = 0x00000000;
	EPwm2Regs.CMPA.all  = 0x00000000;
	EPwm3Regs.CMPA.all  = 0x00000000;
	EPwm4Regs.CMPA.all  = 0x00000000;
	EPwm5Regs.CMPA.all  = 0x00000000;
	EPwm6Regs.CMPA.all  = 0x00000000;
	EPwm7Regs.CMPA.all  = 0x00000000;
	EPwm8Regs.CMPA.all  = 0x00000000;
	EPwm9Regs.CMPA.all  = 0x00000000;
	EPwm10Regs.CMPA.all = 0x00000000;
	EPwm11Regs.CMPA.all = 0x00000000;

	/*** Set Compare B values ***/
	EPwm1Regs.CMPB.all  = 0x00000000;
	EPwm2Regs.CMPB.all  = 0x00000000;
	EPwm3Regs.CMPB.all  = 0x00000000;
	EPwm4Regs.CMPB.all  = 0x00000000;
	EPwm5Regs.CMPB.all  = 0x00000000;
	EPwm6Regs.CMPB.all  = 0x00000000;
	EPwm7Regs.CMPB.all  = 0x00000000;
	EPwm8Regs.CMPB.all  = 0x00000000;
	EPwm9Regs.CMPB.all  = 0x00000000;
	EPwm10Regs.CMPB.all = 0x00000000;
	EPwm11Regs.CMPB.all = 0x00000000;

	/*** Set Compare C values ***/
//	EPwm1Regs.CMPC  = 0x0000;	// (Unused) Setting Default.
//	EPwm2Regs.CMPC  = 0x0000;	// (Unused) Setting Default.
//	EPwm3Regs.CMPC  = 0x0000;	// (Unused) Setting Default.
//	EPwm4Regs.CMPC  = 0x0000;	// (Unused) Setting Default.
	EPwm5Regs.CMPC  = 0x01E7;	// 0x01E7(4.87us)
	EPwm6Regs.CMPC  = 0x01E7;
	EPwm7Regs.CMPC  = 0x01E7;
	EPwm8Regs.CMPC  = 0x01E7;
//	EPwm9Regs.CMPC  = 0x0000;   // (Unused) Setting Default.
//	EPwm10Regs.CMPC = 0x0000;   // (Unused) Setting Default.
//	EPwm11Regs.CMPC = 0x0000;   // (Unused) Setting Default.

	/*** Setup counter mode ***/
	EPwm1Regs.TBCTL.all  = 0x2012;
	EPwm2Regs.TBCTL.all  = 0x2006;
	EPwm3Regs.TBCTL.all  = 0x2006;
	EPwm4Regs.TBCTL.all  = 0x2006;
	EPwm5Regs.TBCTL.all  = 0x2006;
	EPwm6Regs.TBCTL.all  = 0x0006;
	EPwm7Regs.TBCTL.all  = 0x0006;
	EPwm8Regs.TBCTL.all  = 0x2006;
	EPwm9Regs.TBCTL.all  = 0x2006;
	EPwm10Regs.TBCTL.all = 0x0006;
	EPwm11Regs.TBCTL.all = 0x2002;

	/*** Setup shadowing ***/
	EPwm1Regs.CMPCTL.all  = 0x0000;
	EPwm2Regs.CMPCTL.all  = 0x0000;
	EPwm3Regs.CMPCTL.all  = 0x0000;
	EPwm4Regs.CMPCTL.all  = 0x000F;
	EPwm5Regs.CMPCTL.all  = 0x000A;
	EPwm6Regs.CMPCTL.all  = 0x000A;
	EPwm7Regs.CMPCTL.all  = 0x000A;
	EPwm8Regs.CMPCTL.all  = 0x000A;
	EPwm9Regs.CMPCTL.all  = 0x0000;
	EPwm10Regs.CMPCTL.all = 0x0000;
	EPwm11Regs.CMPCTL.all = 0x0000;

	/*** Set actions A ***/
	EPwm1Regs.AQCTLA.all  = 0x0090;
	EPwm2Regs.AQCTLA.all  = 0x0090;
	EPwm3Regs.AQCTLA.all  = 0x0090;
	EPwm4Regs.AQCTLA.all  = 0x0000;		// (Unused) Setting Default.
	EPwm5Regs.AQCTLA.all  = 0x0090;
	EPwm6Regs.AQCTLA.all  = 0x0090;
	EPwm7Regs.AQCTLA.all  = 0x0090;
	EPwm8Regs.AQCTLA.all  = 0x0090;
	EPwm9Regs.AQCTLA.all  = 0x0090;
	EPwm10Regs.AQCTLA.all = 0x0090;
	EPwm11Regs.AQCTLA.all = 0x0090;

	/*** Set actions B ***/
	EPwm1Regs.AQCTLB.all  = 0x0600;
	EPwm2Regs.AQCTLB.all  = 0x0600;
	EPwm3Regs.AQCTLB.all  = 0x0600;
	EPwm4Regs.AQCTLB.all  = 0x0090;
	EPwm4Regs.AQCTLB.all  = 0x0006;
	EPwm5Regs.AQCTLB.all  = 0x0600;
	EPwm6Regs.AQCTLB.all  = 0x0600;
	EPwm7Regs.AQCTLB.all  = 0x0600;
	EPwm8Regs.AQCTLB.all  = 0x0600;
	EPwm9Regs.AQCTLB.all  = 0x0000;     // (Unused) Setting Default.
	EPwm10Regs.AQCTLB.all = 0x0000;     // (Unused) Setting Default.
	EPwm11Regs.AQCTLB.all = 0x0000;		// (Unused) Setting Default.

	/***
	 * Enable HR res operation
	 *  EPwm9~12 HR non-compatible channel.
	 ***/
//	EPwm1Regs.HRCNFG.all  = 0x0000;     // (Unused) Setting Default.
//	EPwm2Regs.HRCNFG.all  = 0x0000;     // (Unused) Setting Default.
//	EPwm3Regs.HRCNFG.all  = 0x0000;     // (Unused) Setting Default.
//	EPwm4Regs.HRCNFG.all  = 0x0000;     // (Unused) Setting Default.
#ifdef SELECT_HRPWM
	EPwm5Regs.HRCNFG.all  = 0x1353;
	EPwm6Regs.HRCNFG.all  = 0x1353;
	EPwm7Regs.HRCNFG.all  = 0x1353;
	EPwm8Regs.HRCNFG.all  = 0x1353;
#endif

//	EPwm1Regs.HRCNFG2.all = 0x0000;     // (Unused) Setting Default.
//	EPwm2Regs.HRCNFG2.all = 0x0000;     // (Unused) Setting Default.
//	EPwm3Regs.HRCNFG2.all = 0x0000;     // (Unused) Setting Default.
//	EPwm4Regs.HRCNFG2.all = 0x0000;     // (Unused) Setting Default.
#if SELECT_HRPWM
	EPwm5Regs.HRCNFG2.all = 0x0003;
	EPwm6Regs.HRCNFG2.all = 0x0003;
	EPwm7Regs.HRCNFG2.all = 0x0003;
	EPwm8Regs.HRCNFG2.all = 0x0003;
#endif

//	EPwm1Regs.HRPCTL.all  = 0x0000;     // (Unused) Setting Default.
//	EPwm2Regs.HRPCTL.all  = 0x0000;     // (Unused) Setting Default.
//	EPwm3Regs.HRPCTL.all  = 0x0000;     // (Unused) Setting Default.
//	EPwm4Regs.HRPCTL.all  = 0x0000;     // (Unused) Setting Default.
#if SELECT_HRPWM
	EPwm5Regs.HRPCTL.all  = 0x0005;
	EPwm6Regs.HRPCTL.all  = 0x0005;
	EPwm7Regs.HRPCTL.all  = 0x0005;
	EPwm8Regs.HRPCTL.all  = 0x0005;
#endif

	/***
	 * Interrupt where we will change the Compare Values
	 ***/
	EPwm1Regs.ETSEL.all  = 0x0900;
//	EPwm2Regs.ETSEL.all  = 0x0000;      // (Unused) Setting Default.
//	EPwm3Regs.ETSEL.all  = 0x0000;      // (Unused) Setting Default.
//	EPwm4Regs.ETSEL.all  = 0x0000;      // (Unused) Setting Default.
	EPwm5Regs.ETSEL.all  = 0x0C10;
	EPwm6Regs.ETSEL.all  = 0x0C10;
	EPwm7Regs.ETSEL.all  = 0x0C10;
	EPwm8Regs.ETSEL.all  = 0x0C10;
//	EPwm9Regs.ETSEL.all  = 0x0000;      // (Unused) Setting Default.
//	EPwm10Regs.ETSEL.all = 0x0000;      // (Unused) Setting Default.
//	EPwm11Regs.ETSEL.all = 0x0000;      // (Unused) Setting Default.

	EPwm1Regs.ETPS.all  = 0x0100;
//	EPwm2Regs.ETPS.all  = 0x0000;       // (Unused) Setting Default.
//	EPwm3Regs.ETPS.all  = 0x0000;       // (Unused) Setting Default.
//	EPwm4Regs.ETPS.all  = 0x0000;       // (Unused) Setting Default.
	EPwm5Regs.ETPS.all  = 0x0100;
	EPwm6Regs.ETPS.all  = 0x0100;
	EPwm7Regs.ETPS.all  = 0x0100;
	EPwm8Regs.ETPS.all  = 0x0100;
//	EPwm9Regs.ETPS.all  = 0x0000;       // (Unused) Setting Default.
//	EPwm10Regs.ETPS.all = 0x0000;       // (Unused) Setting Default.
//	EPwm11Regs.ETPS.all = 0x0000;       // (Unused) Setting Default.

	/***
	 * Dead Time Configuration
	 *  Unused for software support.
	 ***/
#if 0
	EPwm1Regs.DBCTL.all  = 0x0000;
	EPwm2Regs.DBCTL.all  = 0x0000;
	EPwm3Regs.DBCTL.all  = 0x0000;
	EPwm4Regs.DBCTL.all  = 0x0000;
	EPwm5Regs.DBCTL.all  = 0x0000;
	EPwm6Regs.DBCTL.all  = 0x0000;
	EPwm7Regs.DBCTL.all  = 0x0000;
	EPwm8Regs.DBCTL.all  = 0x0000;
	EPwm9Regs.DBCTL.all  = 0x0000;
	EPwm10Regs.DBCTL.all = 0x0000;
	EPwm11Regs.DBCTL.all = 0x0000;

	EPwm1Regs.DBRED.bit.DBRED  = 0x0000;
	EPwm2Regs.DBRED.bit.DBRED  = 0x0000;
	EPwm3Regs.DBRED.bit.DBRED  = 0x0000;
	EPwm4Regs.DBRED.bit.DBRED  = 0x0000;
	EPwm5Regs.DBRED.bit.DBRED  = 0x0000;
	EPwm6Regs.DBRED.bit.DBRED  = 0x0000;
	EPwm7Regs.DBRED.bit.DBRED  = 0x0000;
	EPwm8Regs.DBRED.bit.DBRED  = 0x0000;
	EPwm9Regs.DBRED.bit.DBRED  = 0x0000;
	EPwm10Regs.DBRED.bit.DBRED = 0x0000;
	EPwm11Regs.DBRED.bit.DBRED = 0x0000;

	EPwm1Regs.DBFED.bit.DBFED  = 0x0000;
	EPwm2Regs.DBFED.bit.DBFED  = 0x0000;
	EPwm3Regs.DBFED.bit.DBFED  = 0x0000;
	EPwm4Regs.DBFED.bit.DBFED  = 0x0000;
	EPwm5Regs.DBFED.bit.DBFED  = 0x0000;
	EPwm6Regs.DBFED.bit.DBFED  = 0x0000;
	EPwm7Regs.DBFED.bit.DBFED  = 0x0000;
	EPwm8Regs.DBFED.bit.DBFED  = 0x0000;
	EPwm9Regs.DBFED.bit.DBFED  = 0x0000;
	EPwm10Regs.DBFED.bit.DBFED = 0x0000;
	EPwm11Regs.DBFED.bit.DBFED = 0x0000;
#endif

	/***
	 * EPwm Trip configuration.
	 ***/
	EPwm1Regs.TZSEL.all  = 0x0000;
	EPwm2Regs.TZSEL.all  = 0x0000;
	EPwm3Regs.TZSEL.all  = 0x0000;
	EPwm4Regs.TZSEL.all  = 0x0000;
	EPwm5Regs.TZSEL.all  = 0x0000;
	EPwm6Regs.TZSEL.all  = 0x0000;
	EPwm7Regs.TZSEL.all  = 0x0000;
	EPwm8Regs.TZSEL.all  = 0x0000;
	EPwm9Regs.TZSEL.all  = 0x0000;
	EPwm10Regs.TZSEL.all = 0x0000;
	EPwm11Regs.TZSEL.all = 0x0000;

	EPwm1Regs.TZDCSEL.all  = 0x0618;
	EPwm2Regs.TZDCSEL.all  = 0x0618;
	EPwm3Regs.TZDCSEL.all  = 0x0618;
	EPwm4Regs.TZDCSEL.all  = 0x0600;    // Use only EPwmxB
	EPwm5Regs.TZDCSEL.all  = 0x0618;
	EPwm6Regs.TZDCSEL.all  = 0x0618;
	EPwm7Regs.TZDCSEL.all  = 0x0618;
	EPwm8Regs.TZDCSEL.all  = 0x0618;
	EPwm9Regs.TZDCSEL.all  = 0x0018;    // Use only EPwmxA
	EPwm10Regs.TZDCSEL.all = 0x0018;    // Use only EPwmxA
	EPwm11Regs.TZDCSEL.all = 0x0018;    // Use only EPwmxA

	EPwm1Regs.TZCTL.all  = 0x0BBA;
	EPwm2Regs.TZCTL.all  = 0x0BBA;
	EPwm3Regs.TZCTL.all  = 0x0BBA;
	EPwm4Regs.TZCTL.all  = 0x0FFF;      // No Trip
	EPwm5Regs.TZCTL.all  = 0x0BBA;
	EPwm6Regs.TZCTL.all  = 0x0BBA;
	EPwm7Regs.TZCTL.all  = 0x0BBA;
	EPwm8Regs.TZCTL.all  = 0x0BBA;
	EPwm9Regs.TZCTL.all  = 0x0FBE;      // Use only EPwmxA
	EPwm10Regs.TZCTL.all = 0x0FBE;      // Use only EPwmxA
	EPwm11Regs.TZCTL.all = 0x0FBE;      // Use only EPwmxA

	EPwm1Regs.DCTRIPSEL.all  = 0x0F0F;
	EPwm2Regs.DCTRIPSEL.all  = 0x0F0F;
	EPwm3Regs.DCTRIPSEL.all  = 0x0F0F;
	EPwm4Regs.DCTRIPSEL.all  = 0x0FFF;  // Use only EPwmxB
	EPwm5Regs.DCTRIPSEL.all  = 0x0F0F;
	EPwm6Regs.DCTRIPSEL.all  = 0x0F0F;
	EPwm7Regs.DCTRIPSEL.all  = 0x0F0F;
	EPwm8Regs.DCTRIPSEL.all  = 0x0F0F;
	EPwm9Regs.DCTRIPSEL.all  = 0xFF0F;  // Use only EPwmxA
	EPwm10Regs.DCTRIPSEL.all = 0xFF0F;  // Use only EPwmxA
	EPwm11Regs.DCTRIPSEL.all = 0xFF0F;  // Use only EPwmxA

	// SYNC_SOC
	SyncSocRegs.ADCSOCOUTSELECT.all = 0x00000010;

	// Input_Xber
	InputXbarRegs.INPUT1SELECT  = 0x0019;
	InputXbarRegs.INPUT13SELECT = 0x0043;
	InputXbarRegs.INPUT14SELECT = 0x0044;

	// OutputXbar
	OutputXbarRegs.OUTPUT1MUX0TO15CFG.bit.MUX13 = 1;
	OutputXbarRegs.OUTPUT1MUXENABLE.bit.MUX13 = 1;

	EDIS;
}

0 Ryan Ma over 3 years ago in reply to naoki takahashi

TI__Mastermind 27736 points

Hi Naoki,

Are you using SFO library in addition the auto conv?

Best,

Ryan Ma

0 naoki takahashi over 3 years ago in reply to Ryan Ma

Prodigy 40 points

Hi Ryan,

I am using SFO library in addition the auto conv.

Best regards,
Takahashi

0 Ryan Ma over 3 years ago in reply to naoki takahashi

TI__Mastermind 27736 points

Hi Naoki,

Are you sure there are no other possible sources of noise when scoping your PWM output pins?

Best,

Ryan Ma

0 naoki takahashi over 3 years ago in reply to Ryan Ma

Prodigy 40 points

Hi Ryan,

I am sure no other possible sources of noise when scoping the PWM output pins.

Best regards,
Takahashi

0 Ryan Ma over 3 years ago in reply to naoki takahashi

TI__Mastermind 27736 points

Hi Naoki,

Could you configure your TBCTL/DB control registers first before configuring other registers in your header file. Order will matter when configuring PWM registers, see if this can help you out.

Best,

Ryan Ma

0 naoki takahashi over 3 years ago in reply to Ryan Ma

Prodigy 40 points

Hi Ryan,

I am executing SOF() like the code below, but is there any problem in using it?

(It is executed every time, not once every several tens of seconds.)

Best regards,
Takahashi

Fullscreen 78111.main.c Download

//*****************************************************************************
// Start of main
//*****************************************************************************
void main(void)
{
	int status;

	status = SFO_INCOMPLETE;
	while(status== SFO_INCOMPLETE)
	{
		status = SFO();
		if (status == SFO_ERROR)
		{
			/* Error */
		}
	}

//%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
//%%%%%%%%%%%INFINITE LOOP%%%%%%%%%
//%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
	for(;;)
	{
		status = SFO();
		if (status == SFO_ERROR)
		{
			/* Error */
		}
	}
}

0 Ryan Ma over 3 years ago in reply to naoki takahashi

TI__Mastermind 27736 points

Hi Naoki,

This is the correct way to run SFO, the outputs you're seeing on the oscillscope don't seem to align with what could happen unless your trip zone is being cleared during operation.

Is this output replicable? Are you clearing the trip zone flag during HRPWM operation? I cannot seem to replicate the issue you're seeing.

Best,

Ryan Ma

0 naoki takahashi over 2 years ago in reply to Ryan Ma

Prodigy 40 points

Hi Ryan,

I understand that there is nothing wrong with using SOF().

I'm not clearing the trip zone flag during operation.

C2000™︎ microcontrollers

C2000 microcontrollers forum

TMS320F28375D: about hrpwm operation