TMS320F28378S: Power sequencing

Samuel Compton

Part Number: TMS320F28378S

Hi,

We are designing for TMS320F28378SPZP (100-pin QFP).

We see in the datasheet "During the ramp, VDD should be kept no more than 0.3 V above VDDIO". VDDIO is typically 3.3V, VDD is typically 1.2V. Is it therefore acceptable to power up all 3.3V supplies and then all 1.2V supplies?

We are using two separate DC / DC converters to originate 3.3V and 1.2V. In our current design, the 3.3V converter PGOOD signal drives the enable line on the 1.2V converter; 1.2V does not power on until 3.3V powers on. Is this acceptable?

Thanks!

over 2 years ago

0 Hareesh Janakiraman over 2 years ago

TI__Guru* 95315 points

Note that VDDOSC is a 3.3v supply pin and the datasheet says the below:

VDDOSC and VDD must be powered on and off at the same time. VDDOSC should not be powered on when VDD is off. For applications not powering VDDOSC and VDD at the same time, see the "INTOSC: VDDOSC Powered Without VDD Can Cause INTOSC Frequency Drift" advisory in the TMS320F2837xD Dual-Core MCUs Silicon Errata

The above implies that VDD should ramp along with 3.3v.

0 Samuel Compton over 2 years ago in reply to Hareesh Janakiraman

Prodigy 60 points

Hi Hareesh,

Thank you for your message. Do TMS320F2837XS parts typically require a linear voltage regulator or is the voltage ripple typical of an SMPS adequate for these parts? I do not see a specification for supply voltage regulation in the datasheet.

THanks!

0 Hareesh Janakiraman over 2 years ago in reply to Samuel Compton

TI__Guru* 95315 points

Samuel,

I am closing this thread since you asked the same question in the other thread.

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TMS320F28378S: Power sequencing