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TMS320F280039C: 1.2 VDD ramp slope

Vincenzo Pizzolante
Mastermind 25866 points
Part Number: TMS320F280039C


hi

on page 79 of the F28003x DS we state the slope for the VDD ramp (3-10 to 100mV/usec).

how seriously we have to take these limits? normally SMPS are slower.

Would that be a problem (I guess not, just to be 500% sure)

thanks a lot in advance

KR

Vincenzo

  • 0
    TI__Guru* 81560 points

    Vincenzo,

    I believe the min ramp time is to guardband the VDDPOR logic to keep reset held until it reaches 1.14V(Vmin).  The release point for the VDDPOR is 1V, so the slower the ramp rate the more risk there is that XRSn is released with VDD out of spec.

    With that said, if you have an external supervisor, this aspect is moot since that will hold reset active until the voltage targets are met.

    VDDIO rail also has a POR/BOR on it, depending on the relationship you have between VDDIO/VDD, that may provide some protection against the above.  Let me know if you have more questions.

    Best,

    Matthew