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TMS320F28388D: TMS320F28388D: Memory Access Violation

Ivan Gaglioti
Prodigy 60 points
Part Number: TMS320F28388D


Good day,

in regards of "CPU Write Protection" the TRM of TMS320F28388D states .. "Also, an access violation interrupt is generated if enabled in the interrupt enable register."

I successfully enabled the CPU (Master) Protection and successfully tested that writing to a specific memory address (I´ve tested GS15) doesn´t work (as expected) and I can also retrieve the address which caused the memory violation (MCPUWRAVADDR). 

Now my question: how can I catch the violation/generate an interrupt to get notified of this event? I´ve enabled the CPU Write Master Access Violation Interrupt through the MAVINTEN register but no interrupt is generated. 

Furthermore, I can see that TMS320F2837xD seems having an interrupt INT12.12 (RAM_ACCESS_VIOLATION) which aims to handle this kind of interrupt, whereas TMS320F28388D seems  not having such "feature".

Please let me know whether and how I can generate an interrupt  upon a CPU Write access violation.

Thank you

Ivan

  • 0
    TI__Guru** 115881 points

    Hi,

    Ivan Gaglioti said:
    Furthermore, I can see that TMS320F2837xD seems having an interrupt INT12.12 (RAM_ACCESS_VIOLATION) which aims to handle this kind of interrupt, whereas TMS320F28388D seems it doesn´t have such "feature".

    On this device all these errors are combined into SYS_ERR (INT1.10). Please refer section "3.4.6 System Error and CM Status Interrupts" in TRM for more detail.

    Regards,

    Vivek Singh

  • 0 in reply to Vivek Singh
    Prodigy 60 points
    Vivek Singh said:
    On this device all these errors are combined into SYS_ERR (INT1.10). Please refer section "3.4.6 System Error and CM Status Interrupts" in TRM for more detail.

    Hi Vivek,

    thank you very much for your feedback.

    Yes, your hint definitely leads me to the right direction.

    However, I´m having some issues with SYS_ERR. I can see always the related Group 1 interrupt active and triggered and this is due to AUX_PLL_SLIP (see attached image).

    Once I clear it the interrupt , it is not generated again for a while until it comes again. It looks a spurious interrupt coming time to time.

    This leads the runtime to call always my interrupt handler installed to manage INT1.10 (SYS_ERR interrupt)

    My understanding is that a SYS_ERR sub-interrupt can be "masked" (and thus disabled) by mean of SYS_ERR_MASK and that AUX_PLL_SLIP should be masked by default => from the TRM: 3.15.18.8 SYS_ERR_MASK Register (Offset = 16h) [Reset = 60h]-

    In the debugger however I observe the following, that is AUX_PLL_SLIP is 0.

    Since there´s a note in the TRM "Note: This bit must always be set to 1." I thought I need to do it manually but it doesn´t work. It seems that writing this register has not effect even if I try to manipulate it directly in the debugger.

    This is the snippet code I use:

        EALLOW;
        *SYS_ERR_MASK = 0x60;
        EDIS;
    Do you have any idea how to "disable" the generation of AUX_PLL_SLIP interrupt?
    [UPDATE]
    The problem is also that since at the instant the my code to provoke a RAM_ACC_VIOL is executed, AUX_PLL_SLIP is already enabled (and thus GINT as well), and this leads to not having the RAMM_ACC_VIOL interrupt raised even though the correspondent SYS_ERR_INT_FLG is set to 1. The only way is to manually clear the GINT just an instant before executing the code provoking RAM_ACC_VIOL, but this is done in the debugger and manually..
     
    Thank you
    Ivam
  • +1 in reply to Ivan Gaglioti
    TI__Guru** 115881 points

    Hi,

    Ivan Gaglioti said:

    This is the snippet code I use:

        EALLOW;
        *SYS_ERR_MASK = 0x60;
        EDIS;
    Do you have any idea how to "disable" the generation of AUX_PLL_SLIP interrupt?

    Please see below detail of KEY field of this register -

    Please write the value along with correct KEY value and that should fix the issue.

    Regards,

    Vivek Singh

  • 0 in reply to Vivek Singh
    Prodigy 60 points

    Awesome. I overlooked this. Thank you so much.