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TMS320F28388D: SCI Errors Handling

Lawrence Wong
Genius 16580 points

Part Number: TMS320F28388D

Customer reports having SCI Framing errors. The problem is that PE and BRKDT has been detected by the hardware:

They discovered that after problem occurred no more data is received (RX FIFO is empty all the time), although the transmission is ongoing. They can see that they can recover from this state by SCI re-initialization.

 

Question they have :

  1. Is it normal behavior? Does SCI stops receiving data if RXERROR is set?
  2. Is there any recommendation how to handle such case? Is SCI reset the only option?
  • 0
    TI__Mastermind 28580 points

    Hi Lawrence,

    The FIFO should still receive data if an error interrupt has not been serviced, however only an SCI reset can reset the PE and FE bits.

    Can you verify the customer is setting SCIFFTX to enable the FIFO? Note that this bit is reset after SCIRST is set.

    Thank you,

    Luke

  • 0 in reply to Luke Jones
    TI__Genius 16580 points

    Customer reports:

    ===========

     

    I cannot see anything weird in both SCIFFTX as well as in SCIFFRX registers:

    But transmission is ongoing and RXFFST is equal to 0 all the time. I can recover by SCI re-initialization.

     

    I will continue the investigation and let you know if any finding. Although, I will appreciate any feedback from you.

    =====================

    Regards,

    Lawrence

  • 0 in reply to Lawrence Wong
    TI__Mastermind 28580 points

    Hi Lawrence.

    I may have miscommunicated in my original reply. In my communications with other SCI experts, I referred to the following statement:

    "SCI can receive data further even with error interrupt un-serviced (recommended to use FIFO to store the incoming data)".

    However we have this excerpt in the SCI registers regarding break detects:

    "The SCI sets this bit when a break condition occurs. A break condition occurs when the SCI receiver data line (SCIRXD) remains continuously low for at least 9.625 bits, beginning after a missing first stop bit. The occurrence of a break causes a receiver interrupt to be generated if the RX/BK INT ENA bit is a 1, but it does not cause the receiver buffer to be loaded. A BRKDT interrupt can occur even if the receiver SLEEP bit is set to 1. BRKDT is cleared by an active SW RESET or by a system reset. It is not cleared by receipt of a character after the break is detected. In order to receive more characters, the SCI must be reset by toggling the SW RESET bit or by a system reset."

    An SCI reset is necessary to continue receiving data, however this reset can occur within the ISR servicing the interrupt, causing the SCI to continue receiving data before the interrupt is acknowledged at the end of the ISR.

    Based on this excerpt from the SCI registers, this is expected behavior and an SCI reset is required to continue receiving data after a break detect.

    Let me know if you have any other questions.

    --Luke