TMS320F28386D: SOC counter incremented twice

Hi Steven,

Does this only occur on the very first PWM cycle, or repeatedly? If it only occurs on the first cycle, does initializing the TBCTR at 1 instead of 0 resolve this issue?

Thank you,

Luke

Hi Luke,

Thanks for your reply. It does only occur on the very first PWM cycle. If I set the initial TBCTR of the EPWM module, which generates the sync pulses, to 1 then it does not happen, which is understandable because it reaches zero before the other module. But this is not really a desirable initialization. For me it is not clear, why it happens although all counters are started synchronously and it happens only after the first cycle.

Regards,

Steven

Hi Steven,

I understand this is not a desirable initialization, I was more-so just trying to get more information about what was going on in your system by testing initializing the counter at 1 instead of 0.

It is strange that the skipping only occurs on SOCBCNT and not SOCACNT. Is there any difference in the configurations of SOCA event counter and SOCB event counter? This may help us identify the root cause of the skipping.

Thank you,

Luke

If the SOCA and SOCB configurations are the same, I would be happy to look at your full EPWM configuration code to determine what else the issue may be.

Hi Luke,

I'm sorry, I did not mention that the SOCA event is on CTR=PRD and the SOCB event on CTR=ZERO. For the SOCA event, everything works fine.

Regards,

Steven

Hi Steven, understood. It would make sense this issue does not occur on SOCA then since the sync event would not induce a CTR=TBPRD event.

This would not reveal the root cause of this issue, but another workaround would be to initialize your SOCBCNT at 2 instead of 3.

Could you share your EPWM initialization code or .syscfg file to help determine the root cause of this issue? It may be due to the sequence of when you write to particular registers as well, I would experiment with different combinations of these as well.

Thank you,

Luke

Hi Luke,

Yes that would also be a workaround, but also not desirable.

Attached you find a dummy project, with that I could also reconstruct this error. You also find a picture of the logging in the folder.

I would appreciate if you could test this and give me a feedback about this issue.

Thanks,

Steven

SOC_Increment_Dummy_Project.zip

Hi Steven,

I believe this issue is due to a delay between when EPWM1 TBCTR=0 and when the sync event reaches EPWM4 SYNCIN. On the first cycle, EPWM1 and EPWM4 will be perfectly in sync and the next time TBCTR=0 for both modules will occur simultaneously.

By the time the sync event reaches EPWM4, TBCTR will have already passed 0 for both modules and have a value of at least 1(we have proved this with our earlier test of initializing EPWM4 TBCTR at 1). When the sync event takes effect for EPWM4, it's counter will go down from 1 to 0, and be slightly out of sync with EPWM1. The SOCB counter will also increment a second time unexpectedly. This only happens on the first cycle because EPWM4 is now behind EPWM1, so when the next sync event takes effect for EPWM4 SYNCIN, EPWM1 TBCTR will be 1 and EPWM4 TBCTR will be 0, so EPWM4 SOCB counter will only increment once as expected.

To resolve this, you could set EPWM4 TBPHS to 1, so that it will be perfectly in sync with EPWM1, and the sync event will never reset EPWM4's TBCTR from 1 to 0.

Before you do this however, can you zoom in on your EPWM1 and EPWM4 waveforms to see if they are slightly out of sync? This will prove that the EPWM1 TBCTR is ahead of EPWM4 TBCTR, and a TBPHS of 1 is necessary to perfectly sync the two modules.

Hi Luke,

Thank you for your effort and your answer. I have plotted the difference between the two TBCTR and we can see that in the first cycle, the EPWM4 TBCTR is more ahead than after the first sync event. So this conclusion of you makes sense to me. The mean difference comes because the EPWM1 is read before the EPWM4 counter, so the EPWM4 counter is slightly further.