Hello,
Trying to get a handle on how to properly analyze the output accuracy of the CMPSS DACs.
Can the plots in the figures provided for "CMPSS DAC Static Offset", "CMPSS DAC Static Linearity", and "CMPSS DAC Static Linearity" be used to determine an expected output (because of error) for any programmed value (from 0 to 4095 LSBs)?
I am slightly confused because the electrical characteristics table reports a maximum offset error of 25mV, the figure directly below it indicates that if the DAC is programmed for 0 LSBs the actual output (because of offset error) will be ~300 LSBs. If the reference voltage is 3.3V this means the maximum offset error is actually ~240mV considering the 12-bit resolution.
Sorry if I am interpreting this incorrectly, thank you for any clarification on the matter!
-Josh
