TMS320F28069: Using copy tables with CLA / Expanding CLA program memory / CLA memory optimization / Not enough CLA memory

Hi

I was able to get the code working. run and start addresses mentioned in the linker which i didn't included here. 

i will put the description below to help someone who faced the same issue of running out of CLA program memory. 

The trick was, i had to reprogram the Cla1Regs.MMEMCFG.all bits each time before call copy_in. otherwise, c28 core doesn't have access to Cla program space and copy_in cannot copy the second potion of the program. . 
Following code shows the steps i have followed. 

task 8 is the first task which uses to initialize the cla variables. Task1 is the repeating task, which will be triggered somewhere in the code. 

Cla1Regs.MVECT8 is configured as zero because, for some reason, compiler put that union section at the beginning of the CLA program space and then the rest of the CLA program (Cla1Prog) was placed after that, in the same memory area (RAML3) . Can you Shead a light why that happens. How can we configure, where the code sections are placed in the same memory section. 


Linker code is also included here for the reference. 

EALLOW;

    Cla1Regs.MPISRCSEL1.bit.PERINT1SEL = CLA_INT1_NONE;
    Cla1Regs.MPISRCSEL1.bit.PERINT8SEL = CLA_INT8_NONE;

       memcpy(&cla1Funcs_runstart, &cla1Funcs_loadstart, (Uint32) &cla1Funcs_loadsize);
       memcpy(&mathTablesRunStart, &mathTablesLoadStart, (Uint32) &mathTablesLoadSize);  // load cla math tables for cla sine and cos functions

       EDIS;

       copy_in(&task8_copy_table);
       EALLOW;


       Cla1Regs.MVECT8 = 0;
       Cla1Regs.MPISRCSEL1.bit.PERINT8SEL = CLA_INT8_NONE;
       Cla1Regs.MIER.all = 0x00FF;

       Cla1Regs.MMEMCFG.all = CLA_PROG_ENABLE | CLARAM0_ENABLE | CLARAM1_ENABLE | CLARAM2_ENABLE | CLA_RAM1CPUE;
       Cla1Regs.MCTL.bit.IACKE = 1;
       EDIS;

       Cla1ForceTask8andWait();

       EALLOW;
       Cla1Regs.MIER.all = 0x0000;
       Cla1Regs.MPISRCSEL1.bit.PERINT1SEL = CLA_INT1_NONE;
       Cla1Regs.MMEMCFG.all =0;
       EDIS;


       copy_in(&task1_copy_table);
       EALLOW;
       Cla1Regs.MVECT1 = 0;
       Cla1Regs.MMEMCFG.all = CLA_PROG_ENABLE | CLARAM0_ENABLE | CLARAM1_ENABLE | CLARAM2_ENABLE | CLA_RAM1CPUE;
       Cla1Regs.MIER.all = 0x00FF;
       EDIS;

MEMORY
{
PAGE 0 :   /* Program Memory */
           /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */

   //RAML1       : origin = 0x008800, length = 0x000400     /* on-chip RAM block L1 */
   RAML3       : origin = 0x009000, length = 0x001000	  /* CLA program ram
   OTP         : origin = 0x3D7800, length = 0x000400     /* on-chip OTP */

   FLASHH      : origin = 0x3D8000, length = 0x004000     /* on-chip FLASH */
   FLASHG      : origin = 0x3DC000, length = 0x004000     /* on-chip FLASH */
   FLASHF      : origin = 0x3E0000, length = 0x004000     /* on-chip FLASH */
   FLASHE      : origin = 0x3E4000, length = 0x004000     /* on-chip FLASH */   
   FLASHD      : origin = 0x3E8000, length = 0x004000     /* on-chip FLASH */
   FLASHA      : origin = 0x3EC000, length = 0x007F80     /* on-chip FLASH */
   //FLASHA      : origin = 0x3F4000, length = 0x003F80     /* on-chip FLASH */
   CSM_RSVD    : origin = 0x3F7F80, length = 0x000076     /* Part of FLASHA.  Program with all 0x0000 when CSM is in use. */
   BEGIN       : origin = 0x3F7FF6, length = 0x000002     /* Part of FLASHA.  Used for "boot to Flash" bootloader mode. */
   CSM_PWL_P0  : origin = 0x3F7FF8, length = 0x000008     /* Part of FLASHA.  CSM password locations in FLASHA */

   FPUTABLES   : origin = 0x3FD860, length = 0x0006A0	  /* FPU Tables in Boot ROM */
   IQTABLES    : origin = 0x3FDF00, length = 0x000B50     /* IQ Math Tables in Boot ROM */
   IQTABLES2   : origin = 0x3FEA50, length = 0x00008C     /* IQ Math Tables in Boot ROM */
   IQTABLES3   : origin = 0x3FEADC, length = 0x0000AA	  /* IQ Math Tables in Boot ROM */

   ROM         : origin = 0x3FF3B0, length = 0x000C10     /* Boot ROM */
   RESET       : origin = 0x3FFFC0, length = 0x000002     /* part of boot ROM  */
   VECTORS     : origin = 0x3FFFC2, length = 0x00003E     /* part of boot ROM  */

PAGE 1 :   /* Data Memory */
           /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */
           /* Registers remain on PAGE1                                                  */

   BOOT_RSVD   : origin = 0x000000, length = 0x000050     /* Part of M0, BOOT rom will use this for stack */
   RAMM0       : origin = 0x000050, length = 0x0003B0     /* on-chip RAM block M0 */
   RAMM1       : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
   RAML0L1L2   : origin = 0x008000, length = 0x001000     /* CLA data ram L0 l1 l2 */
  // CLAMSGRAM1  : origin = 0x008C00, length = 0x000200     /* on-chip RAM block L2 */
   //CLAMSGRAM2  : origin = 0x008E00, length = 0x000200     /* on-chip RAM block L2 */

   CLA1_MSGRAMLOW       : origin = 0x001480, length = 0x000080
   CLA1_MSGRAMHIGH      : origin = 0x001500, length = 0x000080


   RAML4       : origin = 0x00A000, length = 0x004000     /* on-chip RAM block L4 */
  // RAML5       : origin = 0x00C000, length = 0x002000     /* on-chip RAM block L5 */
   RAML6       : origin = 0x00E000, length = 0x002000     /* on-chip RAM block L6 */
   RAML7       : origin = 0x010000, length = 0x002000     /* on-chip RAM block L7 */
   RAML8       : origin = 0x012000, length = 0x002000     /* on-chip RAM block L8 */
   USB_RAM     : origin = 0x040000, length = 0x000800     /* USB RAM		  */   
   FLASHB      : origin = 0x3F0000, length = 0x004000     /* on-chip FLASH */     
}




SECTIONS
{
   .scratchpad      : > RAML0L1L2,   PAGE = 1
   .bss_cla		    : > RAML0L1L2,   PAGE = 1
   .const_cla	    : > RAML0L1L2,   PAGE = 1

   /* Allocate program areas: */
   .cinit              : > FLASHA,     PAGE = 0
   .pinit              : > FLASHA,     PAGE = 0
   .text               : > FLASHA,     PAGE = 0
   codestart           : > BEGIN,      PAGE = 0

   ClaToCpuMsgRAM     : > CLA1_MSGRAMLOW,            PAGE = 1                /* Link to PF0 - CLA Message RAM */
   CpuToClaMsgRAM     : > CLA1_MSGRAMHIGH,            PAGE = 1                /* Link to PF0 - CLA Message RAM */


   csmpasswds          : > CSM_PWL_P0, PAGE = 0
   csm_rsvd            : > CSM_RSVD,   PAGE = 0

   /* Allocate uninitalized data sections: */
   .stack              : > RAMM0,      PAGE = 1
   .ebss               : > RAML4,      PAGE = 1
   .esysmem            : > RAML6,      PAGE = 1
   .cio                : > RAML6,      PAGE = 1
   /* Initalized sections to go in Flash */
   /* For SDFlash to program these, they must be allocated to page 0 */
   .econst             : > FLASHA,     PAGE = 0
   .switch             : > FLASHA,     PAGE = 0

   /* Allocate IQ math areas: */
   IQmath              : > FLASHA,     PAGE = 0            /* Math Code */
   IQmathTables        : > IQTABLES,   PAGE = 0, TYPE = NOLOAD
   
   /* Allocate FPU math areas: */
   FPUmathTables       : > FPUTABLES,  PAGE = 0, TYPE = NOLOAD
   
 //  DMARAML5	           : > RAML5,      PAGE = 1
  // DMARAML6	           : > RAML6,      PAGE = 1
  // DMARAML7	           : > RAML7,      PAGE = 1
  // DMARAML8	           : > RAML8,      PAGE = 1


   ramfuncs            : LOAD = FLASHA, PAGE = 0
                         RUN = RAML4,   PAGE = 1
                         LOAD_START(_RamfuncsLoadStart),
                         LOAD_END(_RamfuncsLoadEnd),
                         RUN_START(_RamfuncsRunStart),
                         LOAD_SIZE(_RamfuncsLoadSize)



   dclfuncs		    :    LOAD = FLASHA,  PAGE = 0
                         RUN = RAML4,    PAGE = 1
                         LOAD_START(_DclfuncsLoadStart),
                         LOAD_END(_DclfuncsLoadEnd),
                         RUN_START(_DclfuncsRunStart),
                         LOAD_SIZE(_DclfuncsLoadSize)


   Cla1Prog           :   LOAD = FLASHE, PAGE = 0,            /* Load to flash, run from CLA Prog RAM */
                          RUN_START(_Cla1Prog_Start)
                          RUN = RAML3,       PAGE = 0
                          LOAD_START(_cla1Funcs_loadstart),
                          LOAD_SIZE(_cla1Funcs_loadsize),
                          RUN_START(_cla1Funcs_runstart)

   CLAscratch         : { *.obj(CLAscratch)                              /* Scratchpad memory for the CLA C Compiler */
                          . += CLA_SCRATCHPAD_SIZE;
                          *.obj(CLAscratch_end)
                        } > RAML0L1L2,           PAGE = 1


   CLA1mathTables	: LOAD= FLASHE, PAGE = 0,
                      LOAD_START(_mathTablesLoadStart),
                      LOAD_END(_mathTablesLoadEnd),
                      LOAD_SIZE(_mathTablesLoadSize),
                      RUN = RAML0L1L2,  PAGE = 1
                      RUN_START(_mathTablesRunStart)


   UNION {
    .Cla1Task1 : LOAD = FLASHE PAGE = 0, table (_task1_copy_table)
    .Cla1Task8 : LOAD = FLASHE PAGE = 0, table (_task8_copy_table)
   }RUN = RAML3  PAGE = 0

   .ovly > FLASHE   PAGE = 0

   
   
   .reset              : > RESET,      PAGE = 0, TYPE = DSECT
   vectors             : > VECTORS,    PAGE = 0, TYPE = DSECT

}

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