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TMS320F28377D: EMIF communitcate with FPGA

Ben Qin
Intellectual 2690 points

Part Number: TMS320F28377D

Hi Team,

There is an issue from the customer need your help:

I see that my program uses CS2, which should support asynchronous interfaces

The following is the initialization statement in the program

FPGAs are full of statements like this."

case(Addr)

0x60: dat = current speed

0x61: dat=current location

That is, the FPGA is not configured as RAM, which is this simple return of the desired data according to the address

I still want to ask, except when initializing the GPIO configuration into chip select, read, write, address, there is no need to deal with these later, is it all automatic address mapping? Is it enough to read and write directly to the address?

Thanks & Regards,

Ben

  • 0
    TI__Guru* 95315 points

    Ben,

          I am afraid your question is not clear. Is the MCU reading from (or) writing to the FPGA? Where/how are the variables like dat, current speed, current location defined?

  • 0 in reply to Hareesh Janakiraman
    TI__Intellectual 2690 points

    Hi Hareesh,

    Following is the customer original post:

    I just took over a program involving the communication between 28377d EMIF and FPGA. I read a piece of data from the FPGA. The offset address of this data is 0x0060

    The program is written like this Dat=*(offset address+0x0060)

    Note, it's not the address that bothers me. What I want to ask is:

    When the DSP reads the FPGA, shouldn't the chip select cs be pulled down, the read is valid, and the write is invalid, and the GPIO indicating the address should be output as the address you want to read?

    But I can't see the operation described above in my current program . There are only these codes in the existing program: when reading, take out the data of a certain address; when writing, just write the number to this address.

    (And my understanding is that when I read, I have to do a lot of things to the pins connected to the FPGA (the chip select is pulled low, the read is valid, the write is invalid, and the address I want to read is configured), and then the data in the address is taken)

    Why not focus on other pins like address?

    Thanks & Regards,

    Ben

  • +1 in reply to Ben Qin
    TI__Guru* 95315 points
    Ben Qin said:
    When the DSP reads the FPGA, shouldn't the chip select cs be pulled down, the read is valid, and the write is invalid, and the GPIO indicating the address should be output as the address you want to read?

    Yes, all those things you indicate should happen. Once the EMIF is configured correctly, any access to the CS2 address range should drive those signals automatically. i.e. the code need not do anything explicit.

    Ben Qin said:
    But I can't see the operation described above in my current program . There are only these codes in the existing program: when reading, take out the data of a certain address; when writing, just write the number to this address.

    It is likely the correct address is not being accessed. You need to debug the code on your end.

    Ben Qin said:
    (And my understanding is that when I read, I have to do a lot of things to the pins connected to the FPGA (the chip select is pulled low, the read is valid, the write is invalid, and the address I want to read is configured), and then the data in the address is taken)

    You don't have to anything "manually" for this. The EMIF module drives the pins as needed.

    Ben Qin said:
    Why not focus on other pins like address?

    Sorry I don't understand what you are saying here. 

    I think where you need to focus is whether your code generates the correct address for accessing the FPGA.