TMS320F28388D: there have data for RAM from hex file

Strong ZHANG

Part Number: TMS320F28388D

Hi Expert,

My customer are using F28388D, there have data for the RAM address 0x0003A1EE when generate hex file,

FLASH12 : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */
FLASH13 : origin = 0x0BE000, length = 0x001FF0 /* on-chip Flash */
// FLASH13_RSVD : origin = 0x0BFFF0, length = 0x000010 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */

CPU1TOCPU2RAM : origin = 0x03A000, length = 0x000800
CPU2TOCPU1RAM : origin = 0x03B000, length = 0x000800

anything wrong here?

over 2 years ago

0 Omer Amir over 2 years ago

TI__Mastermind 30185 points

Hello Strong,

Can you please send the linker command file (.cmd) and the .map file for the project? Also, can you please clarify the question from the customer?

Best regards,

Omer Amir

0 Strong ZHANG over 2 years ago in reply to Omer Amir

TI__Expert 4430 points

Hi Omer,

Please see the file below:

https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/171/Servo_5F00_Beta.map

https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/171/Servo_5F00_Beta.hex

Fullscreen 2838x_FLASH_CLA_lnk_cpu2.cmd.txt Download

CLA_SCRATCHPAD_SIZE = 0x100;
--undef_sym=__cla_scratchpad_end
--undef_sym=__cla_scratchpad_start

MEMORY
{
   /* BEGIN is used for the "boot to Flash" bootloader mode   */
   BEGIN            : origin = 0x086000, length = 0x000002
   BOOT_RSVD        : origin = 0x000002, length = 0x0001AF     /* Part of M0, BOOT rom will use this for stack */

/*-----------------------------------------------------------*/
/* RAMM0 ~ 1 :CPU1											 */
/*-----------------------------------------------------------*/
   RAMM0            : origin = 0x0001B1, length = 0x00024F
   RAMM1            : origin = 0x000400, length = 0x0003F8     /* on-chip RAM block M1 */
// RAMM1_RSVD       : origin = 0x0007F8, length = 0x000008     /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
/*-----------------------------------------------------------*/
/* RAMD0 ~ 1 :CPU1	Stack									 */
/*-----------------------------------------------------------*/
   RAMD0_1          : origin = 0x00C000, length = 0x001000
// RAMD0            : origin = 0x00C000, length = 0x000800
// RAMD1            : origin = 0x00C800, length = 0x000800

/*-----------------------------------------------------------*/
/* RAMLS0 ~ 5 :CPU1	CLA										 */
/*-----------------------------------------------------------*/
// RAMLS0_to_LS5    : origin = 0x008000, length = 0x003000
   RAMLS0           : origin = 0x008000, length = 0x000800
   RAMLS1_5			: origin = 0x008800, length = 0x002800

// RAMLS1           : origin = 0x008800, length = 0x000800
// RAMLS2           : origin = 0x009000, length = 0x000800
// RAMLS3           : origin = 0x009800, length = 0x000800
// RAMLS4           : origin = 0x00A000, length = 0x000800
// RAMLS5           : origin = 0x00A800, length = 0x000800
   RAMLS6           : origin = 0x00B000, length = 0x000800
   RAMLS7           : origin = 0x00B800, length = 0x000800

/*-----------------------------------------------------------*/
/* RAM for CPU2												 */
/*-----------------------------------------------------------*/
   RAMGS10_15       : origin = 0x017000, length = 0x005FF8
// RAMGS10          : origin = 0x017000, length = 0x001000
// RAMGS11          : origin = 0x018000, length = 0x001000
// RAMGS12          : origin = 0x019000, length = 0x001000
// RAMGS13          : origin = 0x01A000, length = 0x001000
// RAMGS14          : origin = 0x01B000, length = 0x001000
// RAMGS15          : origin = 0x01C000, length = 0x000FF8
// RAMGS15_RSVD     : origin = 0x01CFF8, length = 0x000008     /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */

   /* Flash sectors */
//   FLASH3_13        : origin = 0x080002, length = 0x039FE6  /* on-chip Flash */

//   FLASH0_2         : origin = 0x080002, length = 0x005FFE  /* on-chip Flash */
// FLASH0           : origin = 0x080002, length = 0x001FFE  /* on-chip Flash */
// FLASH1           : origin = 0x082000, length = 0x002000  /* on-chip Flash */
// FLASH2           : origin = 0x084000, length = 0x002000  /* on-chip Flash */
   FLASH3_13        : origin = 0x086002, length = 0x039FE6  /* on-chip Flash */

// FLASH3           : origin = 0x086000, length = 0x002000  /* on-chip Flash */
// FLASH4           : origin = 0x088000, length = 0x008000  /* on-chip Flash */
// FLASH5           : origin = 0x090000, length = 0x008000  /* on-chip Flash */
// FLASH6           : origin = 0x098000, length = 0x008000  /* on-chip Flash */
// FLASH7           : origin = 0x0A0000, length = 0x008000  /* on-chip Flash */
// FLASH8           : origin = 0x0A8000, length = 0x008000  /* on-chip Flash */
// FLASH9           : origin = 0x0B0000, length = 0x008000  /* on-chip Flash */
// FLASH10          : origin = 0x0B8000, length = 0x002000  /* on-chip Flash */
// FLASH11          : origin = 0x0BA000, length = 0x002000  /* on-chip Flash */
// FLASH12          : origin = 0x0BC000, length = 0x002000  /* on-chip Flash */
// FLASH13          : origin = 0x0BE000, length = 0x001FE8  /* on-chip Flash */
   FLASHCHECK		: origin = 0x0BFFE8, length = 0x000008  /* on-chip Flash */
   FLASH13_RSVD     : origin = 0x0BFFF0, length = 0x000010  /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */

/*-----------------------------------------------------------*/
   CPU1TOCPU2RAM1   : origin = 0x03A000, length = 0x0000A0  /* EtherCAT	[128]	 */
   CPU1TOCPU2RAM2   : origin = 0x03A0A0, length = 0x00012C  /* USB		[300]	 */
// CPU1 д��CPU2������
   CPU1TOCPU2Var1		: origin = 0x03A1CC, length = 0x000001		//�����á� ���B ״̬
   CPU1TOCPU2Var2		: origin = 0x03A1CD, length = 0x000001		//�����á� ���B ĸ�ߵ�ѹ
   CPU1TOCPU2Var3		: origin = 0x03A1CE, length = 0x000001		//�����á� ���B ģ���¶�ĸ�ߵ�ѹ
   Adr_MotB_ICCoreTemp	: origin = 0x03A1CF, length = 0x000001		//�����á� ���B ģ���¶�ĸ�ߵ�ѹ
   Adr_MotB_IqFbk		: origin = 0x03A1D0, length = 0x000002		//�����á� ���B Q�ᷴ������
   Adr_MotB_IdFbk		: origin = 0x03A1D2, length = 0x000002		//�����á� ���B D�ᷴ������
   Adr_MotB_QV			: origin = 0x03A1D4, length = 0x000002		//�����á� ���B Q���ѹ
   Adr_MotB_DV			: origin = 0x03A1D6, length = 0x000002		//�����á� ���B D���ѹ

   Adr_MotB_Iu			: origin = 0x03A1D8, length = 0x000002		//�����á� ���B U�����
   Adr_MotB_Iv			: origin = 0x03A1DA, length = 0x000002		//�����á� ���B V�����
   Adr_MotB_Iw			: origin = 0x03A1DC, length = 0x000002		//�����á� ���B W�����
   Adr_MotA_Init		: origin = 0x03A1DE, length = 0x000002		//�����á� ���A ��ʼ����ɱ�־

   Adr_MotB_IuZero		: origin = 0x03A1E0, length = 0x000002		//�����á� ���B U��������
   Adr_MotB_IvZero		: origin = 0x03A1E2, length = 0x000002		//�����á� ���B V��������
   Adr_MotB_IwZero		: origin = 0x03A1E4, length = 0x000002		//�����á� ���B W��������
   Adr_MotA_Adr			: origin = 0x03A1E6, length = 0x000001		//�����á� ���A 485&Can��ַ
   Adr_Drvier_Type		: origin = 0x03A1E7, length = 0x000001		//�����á� ���A ����������
   Adr_Drvier_ID1		: origin = 0x03A1E8, length = 0x000001		//�����á� ���A �ܳ�1
   Adr_Drvier_ID2		: origin = 0x03A1E9, length = 0x000001		//�����á� ���A �ܳ�2
   Adr_MotB_IAP			: origin = 0x03A1EA, length = 0x000001		//�����á� ���B ����IAP �ܳ�
   Adr_MotB_Boot		: origin = 0x03A1EC, length = 0x000002		//�����á� CPU2 Boot��־
   Adr_MotA_DrvPowType	: origin = 0x03A1EE, length = 0x000001		//�����á� CPU1 ����������


   CPU1TOCPU2RAM3   	: origin = 0x03A1F0, length = 0x000600
/*-----------------------------------------------------------*/
   CPU2TOCPU1RAM1   	: origin = 0x03B000, length = 0x0000A0  /* EtherCAT	[128]	 */
   CPU2TOCPU1RAM2   	: origin = 0x03B0A0, length = 0x00012C  /* USB		[300]	 */


   // CPU2 д��CPU1������
   CPU2TOCPU1Var1		: origin = 0x03B1CC, length = 0x000001		//�����á� ���B ָ��
   CPU2TOCPU1Var2		: origin = 0x03B1CD, length = 0x000001
   CPU2TOCPU1Var3		: origin = 0x03B1CE, length = 0x000001
   CPU2TOCPU1Var4		: origin = 0x03B1CF, length = 0x000001

   CPU2TOCPU1_ACRP		: origin = 0x03B200, length = 0x000040

   CPU2TOCPU1_ACRV		: origin = 0x03B240, length = 0x000010

/*-----------------------------------------------------------*/


// CPUTOCMRAM      		: origin = 0x039000, length = 0x000800
// CMTOCPURAM      		: origin = 0x038000, length = 0x000800

   CANA_MSG_RAM     	: origin = 0x049000, length = 0x000800
   CANB_MSG_RAM     	: origin = 0x04B000, length = 0x000800

   RESET            	: origin = 0x3FFFC0, length = 0x000002

//   CLA1_MSGRAMLOW   	: origin = 0x001480,   length = 0x000080
//   CLA1_MSGRAMHIGH  	: origin = 0x001500,   length = 0x000080
}

SECTIONS
{
   codestart           : > BEGIN, ALIGN(8)
   .text               : > FLASH3_13, ALIGN(8)
   .cinit              : > FLASH3_13, ALIGN(8)
   .switch             : > FLASH3_13, ALIGN(8)
   .reset              : > RESET, TYPE = DSECT /* not used, */
   .stack              : > RAMD0_1

#if defined(__TI_EABI__)
   .init_array      	: > FLASH3_13, ALIGN(8)
   .bss             	: > RAMGS10_15
   .bss:output      	: > RAMLS0
   .data            	: > RAMLS0
   .sysmem          	: > RAMLS0
   /* Initalized sections go in Flash */
   .const           	: > FLASH3_13, ALIGN(8)
#else
   .pinit           	: > FLASH3_13, ALIGN(8)
   .ebss            	: > RAMLS0
   .esysmem         	: > RAMLS0
   /* Initalized sections go in Flash */
   .econst          	: > FLASH3_13, ALIGN(8)
#endif

   MSGRAM1_CPU1_TO_CPU2 : > CPU1TOCPU2RAM1, type=NOINIT
   MSGRAM2_CPU1_TO_CPU2 : > CPU1TOCPU2RAM2, type=NOINIT
   MSGRAM3_CPU1_TO_CPU2 : > CPU1TOCPU2RAM3, type=NOINIT

   MSGRAM1_CPU2_TO_CPU1 : > CPU2TOCPU1RAM1, type=NOINIT
   MSGRAM2_CPU2_TO_CPU1 : > CPU2TOCPU1RAM2, type=NOINIT

   MSGRAM_MotB_ACRP		: > CPU2TOCPU1_ACRP, type=NOINIT
   MSGRAM_MotB_ACRV		: > CPU2TOCPU1_ACRV, type=NOINIT

//   MSGRAM_CPU_TO_CM    : > CPUTOCMRAM, type=NOINIT
//   MSGRAM_CM_TO_CPU    : > CMTOCPURAM, type=NOINIT

   dclfuncs : > FLASH3_13, ALIGN(8)


   #if defined(__TI_EABI__)
       .TI.ramfunc : {} LOAD = FLASH3_13,
                        RUN = RAMLS1_5,
                        LOAD_START(RamfuncsLoadStart),
                        LOAD_SIZE(RamfuncsLoadSize),
                        LOAD_END(RamfuncsLoadEnd),
                        RUN_START(RamfuncsRunStart),
                        RUN_SIZE(RamfuncsRunSize),
                        RUN_END(RamfuncsRunEnd),
                        ALIGN(8)
   #else
       .TI.ramfunc : {} LOAD = FLASH3_13,
                        RUN = RAMLS1_5,
                        LOAD_START(_RamfuncsLoadStart),
                        LOAD_SIZE(_RamfuncsLoadSize),
                        LOAD_END(_RamfuncsLoadEnd),
                        RUN_START(_RamfuncsRunStart),
                        RUN_SIZE(_RamfuncsRunSize),
                        RUN_END(_RamfuncsRunEnd),
                        ALIGN(8)
   #endif

}

/*
//===========================================================================
// End of file.
//===========================================================================
*/

0 Omer Amir over 2 years ago in reply to Strong ZHANG

TI__Mastermind 30185 points

Hello Strong,

Can you please answer my second question? I'm not familiar enough with the format of the hex file to be able to tell if something's wrong or if there's just a question. Can you give me some context as to what the user is asking?

Best regards,

Omer Amir

0 Strong ZHANG over 2 years ago in reply to Omer Amir

TI__Expert 4430 points

Omer,

as customer feedback, hex file should not contain data from RAM address, but hex file that he provide contain data from RAM address which is 0x0003A1EE.

could you check if anything wrong for C20000 compiler?

0 Strong ZHANG over 2 years ago in reply to Strong ZHANG

TI__Expert 4430 points

Omer,

from the cmd file, 0x0003A1EE belong to CPU1TOCPU2RAM, which should not be showed in the hex file.

CPU1TOCPU2RAM : origin = 0x03A000, length = 0x000800
CPU2TOCPU1RAM : origin = 0x03B000, length = 0x000800

0 George Mock over 2 years ago in reply to Strong ZHANG

TI__Guru**** 250180 points

The linker map file shows this ...

.TI.bound:DriverPowerType 
*          0    0003a1ee    00000001     
                  0003a1ee    00000001     CLA09_CLAVar.obj (.TI.bound:DriverPowerType)

.TI.bound:MotA_PwmPeriod 
*          0    0003a1ef    00000001     UNINITIALIZED
                  0003a1ef    00000001     CLA09_CLAVar.obj (.TI.bound:MotA_PwmPeriod)

Each group of lines describes one output section. Both of these output sections are 1 word long. The first one corresponds to the problem address 0x0003a1ee. Notice how the word UNINITALIZED is missing. Compare that to the second output section. This means the output section .TI.bound:DriverPowerType is initialized. That's why the hex utility has output for this address.

I don't know why this section is initialized. But I can see it comes from the object file CLA09_CLAVar.obj. So, for the source file CLA09_CLAVar.cla, please follow the directions in the article How to Submit a Compiler Test Case.

Thanks and regards,

-George

0 Strong ZHANG over 2 years ago in reply to George Mock

TI__Expert 4430 points

George，

Thanks for your support. Customer use the below code that cause this issue.

#pragma RETAIN( DriverPowerType )

uint16_t DriverPowerType = 0; 
#pragma LOCATION(DriverPowerType, 0x03A1EE)

if they change to below code, that UNINITALIZED the variable DriverPowerType, then everything is ok

#pragma RETAIN( DriverPowerType )
uint16_t DriverPowerType;              
#pragma LOCATION(DriverPowerType,  0x03A1EE)

actually, this address below to CPU1TOCPU2RAM, which can not be written by CPU2, and customer's hex is generated by CPU2 project,

this may cause the issue.

0 Omer Amir over 2 years ago in reply to Strong ZHANG

TI__Mastermind 30185 points

Hello Strong,

Strong ZHANG said:
actually, this address below to CPU1TOCPU2RAM, which can not be written by CPU2, and customer's hex is generated by CPU2 project,

this may cause the issue.

I'm not sure why this would cause an issue, this message RAM intentionally restricts access so CPU2 can only read or perform debug writes. Are you saying that because the CPU2 cannot write to the CPU1TOCPU2RAM, that the memory location should not be showing up in the hex file? Or is it because the RAM is shared between the CPUs?

Best regards,

Omer Amir

C2000™︎ microcontrollers

C2000 microcontrollers forum

TMS320F28388D: there have data for RAM from hex file