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TMS320F2800157: TMS320F2800157 BOR

kai.shen
Prodigy 10 points
Part Number: TMS320F2800157
Other Parts Discussed in Thread: C2000WARE

If I use BOR to monitor under voltage, I need to verify the function is normal at start up. I wanted to lower the power supply to trigger reset and read the reset source to verify BOR function correct, but I can't distinguish the reason between BOR and external reset, all of them could assert  RESC.XRSn.  could you give me some suggestion?

  • 0
    TI__Guru* 81500 points

    Kai,

    A pure XRSn will only set bit 1 in the RESC register, while a BOR will set both bit 0 and bit 1. 

    However, these are used by the BROM to determine the boot flow, from what I understand the BROM will also clear these bits before passing control to the user code.

    You should be able to test the XRSn bit getting set with the XRSn simulated reset(since you can keep the BROM from running), but I don't believe you will be able to capture a POR event since that will terminate the debug connection and the BROM will clear these before you can read them with the CPU.

    Without the emulator connected, both these bits in RESC will have been cleared by the time the C28x boot passes control to application code.

    I will look into if the BROM stores off the RESC before clearing into its M0 RAM space, I am not sure on this aspect.

    Best,

    Matthew

  • 0 in reply to MatthewPate
    TI__Guru* 81500 points

    Kai,

    The boot ROM will store the reset cause in the Boot_Status variable that is at address 0x0002 in the RAM.

    The bit definitions are in cpu1bootrom.h

    here: C:\ti\c2000\C2000Ware_4_03_00_00\libraries\boot_rom\f280015x\rev0\rom_sources\F280015x_ROM\bootROM\include\cpu1bootrom.h

    Look for

    #define CPU1_BOOTROM_HANDLED_XRSN                       0x00001000UL
    #define CPU1_BOOTROM_HANDLED_POR                        0x00002000UL

    // CPU1 Boot mode status bit field starts from 0 and ends at 7
// It can take any values in the range 0 to 0xFF
//
#define CPU1_BOOTROM_BOOTSTS_SYSTEM_START_BOOT          0x00000001UL  //Set during the initialization phase of the boot ROM
#define CPU1_BOOTROM_BOOTSTS_IN_FLASH_BOOT              0x00000002UL
#define CPU1_BOOTROM_BOOTSTS_IN_SECURE_FLASH_BOOT       0x00000003UL
#define CPU1_BOOTROM_BOOTSTS_IN_PARALLEL_BOOT           0x00000004UL
#define CPU1_BOOTROM_BOOTSTS_IN_RAM_BOOT                0x00000005UL
#define CPU1_BOOTROM_BOOTSTS_IN_SCI_BOOT                0x00000006UL
#define CPU1_BOOTROM_BOOTSTS_IN_SPI_BOOT                0x00000007UL
#define CPU1_BOOTROM_BOOTSTS_IN_I2C_BOOT                0x00000008UL
#define CPU1_BOOTROM_BOOTSTS_IN_CAN_BOOT                0x00000009UL
#define CPU1_BOOTROM_BOOTSTS_IN_MCAN_BOOT               0x0000000AUL
#define CPU1_BOOTROM_BOOTSTS_IN_WAIT_BOOT               0x0000000BUL

#define CPU1_BOOTROM_RAM_INIT_COMPLETE                  0x00000100UL
#define CPU1_BOOTROM_DCSM_INIT_COMPLETE                 0x00000200UL
#define CPU1_BOOTROM_POR_MEM_TEST_COMPLETE              0x00000400UL
#define CPU1_BOOTROM_RESC_HANDLED                       0x00000800UL
#define CPU1_BOOTROM_HANDLED_XRSN                       0x00001000UL
#define CPU1_BOOTROM_HANDLED_POR                        0x00002000UL
#define CPU1_BOOTROM_WATCHDOG_SELFTEST_FAIL             0x00004000UL
#define CPU1_BOOTROM_BOOT_COMPLETE                      0x00008000UL

#define CPU1_BOOTROM_GOT_ITRAP                          0x00010000UL
#define CPU1_BOOTROM_GOT_A_PIE_MISMATCH                 0x00020000UL
#define CPU1_BOOTROM_GOT_AN_ERAD_NMI                    0x00040000UL
#define CPU1_BOOTROM_GOT_A_RL_NMI                       0x00080000UL
#define CPU1_BOOTROM_GOT_A_MEM_UNCERR_NMI               0x00100000UL
#define CPU1_BOOTROM_GOT_A_PIE_REGPARITYERR             0x00200000UL
#define CPU1_BOOTROM_GOT_A_MCLK_NMI                     0x00400000UL
#define CPU1_BOOTROM_GOT_A_LSCMP_NMI                    0x00800000UL

#define BOOTROM_PLL_ENABLE_SUCCESS                      0x01000000UL
#define CPU1_BOOTROM_DCSM_INIT_INVALID_LP               0x02000000UL
#define CPU1_BOOTROM_DCSM_INIT_LP_ERROR_SET             0x04000000UL
#define CPU1_BOOTROM_FLASH_VERIFICATION_ERROR           0x08000000UL
#define CPU1_BOOTROM_RAM_INIT_ERROR                     0x10000000UL
#define CPU1_BOOTROM_TRIM_LOAD_ERROR                    0x20000000UL
#define CPU1_BOOTROM_FLASH_2T_NOT_READY                 0x40000000UL

    Best,

    Matthew