I just happen to run into an issue that I can’t seem to fix. I can’t get the XCLKOUT to clock out at anything faster than ¼ the SYSCLKOUT.
Here is the code I am using.
#define DSP28_DIVSEL 2 // Enable /2 for SYSCLKOUT
#define DSP28_PLLCR 10
void InitSysCtrl(void)
{
// Disable the watchdog
DisableDog();
// Initialize the PLL control: PLLCR and DIVSEL
// DSP28_PLLCR and DSP28_DIVSEL are defined in DSP2833x_Examples.h
InitPll(DSP28_PLLCR,DSP28_DIVSEL);
// Initialize the peripheral clocks
InitPeripheralClocks();
}
void InitPll(Uint16 val, Uint16 divsel)
{
EALLOW;
// Make sure the PLL is not running in limp mode
if (SysCtrlRegs.PLLSTS.bit.MCLKSTS != 0)
{
// Missing external clock has been detected
// Replace this line with a call to an appropriate
// SystemShutdown(); function.
asm(" ESTOP0");
}
// DIVSEL MUST be 0 before PLLCR can be changed from 0x0000.
// It is set to 0 by an external reset XRSn this puts us in 1/4
if (SysCtrlRegs.PLLSTS.bit.DIVSEL != 0)
{
SysCtrlRegs.PLLSTS.bit.DIVSEL = 0;
}
// Change the PLLCR
if (SysCtrlRegs.PLLCR.bit.DIV != val)
{
// Before setting PLLCR turn off missing clock detect logic
SysCtrlRegs.PLLSTS.bit.MCLKOFF = 1;
SysCtrlRegs.PLLCR.bit.DIV = val;;
// Wait for the PLL lock bit to be set.
while(SysCtrlRegs.PLLSTS.bit.PLLLOCKS != 1)
{
// Uncomment to service the watchdog
// ServiceDog();
}
SysCtrlRegs.PLLSTS.bit.MCLKOFF = 0;
}
// If switching to 1/2
if((divsel == 1)||(divsel == 2))
{
SysCtrlRegs.PLLSTS.bit.DIVSEL = divsel;
}
// NOTE: ONLY USE THIS SETTING IF PLL IS BYPASSED (I.E. PLLCR = 0) OR OFF
// If switching to 1/1
// * First go to 1/2 and let the power settle
// The time required will depend on the system, this is only an example
// * Then switch to 1/1
if(divsel == 3)
{
SysCtrlRegs.PLLSTS.bit.DIVSEL = 2;
DELAY_US(50L);
SysCtrlRegs.PLLSTS.bit.DIVSEL = 3;
}
EDIS;
}
void InitPeripheralClocks(void)
{
EALLOW;
// HISPCP/LOSPCP prescale register settings, normally it will be set to default values
SysCtrlRegs.HISPCP.all = 0x0001;
SysCtrlRegs.LOSPCP.all = 0x0002;
// This function is not written to be an example of efficient code.
SysCtrlRegs.PCLKCR0.bit.ADCENCLK = 1; // ADC clock enabled
// *IMPORTANT*
// The ADC_cal function, which copies the ADC calibration values from TI reserved
// OTP into the ADCREFSEL and ADCOFFTRIM registers, occurs automatically in the
// Boot ROM. If the boot ROM code is bypassed during the debug process, the
// following function MUST be called for the ADC to function according
// to specification. The clocks to the ADC MUST be enabled before calling this
// function.
// See the device data manual and/or the ADC Reference
// Manual for more information.
ADC_cal();
SysCtrlRegs.PCLKCR0.bit.I2CAENCLK = 0; // I2C clock off
SysCtrlRegs.PCLKCR0.bit.SCIAENCLK = 0; // SCI-A clock off
SysCtrlRegs.PCLKCR0.bit.SCIBENCLK = 0; // SCI-B clock off
SysCtrlRegs.PCLKCR0.bit.SCICENCLK = 0; // SCI-C clock off
SysCtrlRegs.PCLKCR0.bit.SPIAENCLK = 0; // SPI-A clock off
SysCtrlRegs.PCLKCR0.bit.MCBSPAENCLK = 0; // McBSP-A clock off
SysCtrlRegs.PCLKCR0.bit.MCBSPBENCLK = 0; // McBSP-B clock off
SysCtrlRegs.PCLKCR0.bit.ECANAENCLK=0; // eCAN-A clock off
SysCtrlRegs.PCLKCR0.bit.ECANBENCLK=0; // eCAN-B clock off
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0; // Disable TBCLK within the ePWM
SysCtrlRegs.PCLKCR1.bit.EPWM1ENCLK = 1; // ePWM1 clock on
SysCtrlRegs.PCLKCR1.bit.EPWM2ENCLK = 1; // ePWM2 clock on
SysCtrlRegs.PCLKCR1.bit.EPWM3ENCLK = 1; // ePWM3 clock on
SysCtrlRegs.PCLKCR1.bit.EPWM4ENCLK = 1; // ePWM4 clock on
SysCtrlRegs.PCLKCR1.bit.EPWM5ENCLK = 1; // ePWM5 clock on
SysCtrlRegs.PCLKCR1.bit.EPWM6ENCLK = 1; // ePWM6 clock on
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1; // Enable TBCLK within the ePWM
SysCtrlRegs.PCLKCR1.bit.ECAP3ENCLK = 0; // eCAP3 clock off
SysCtrlRegs.PCLKCR1.bit.ECAP4ENCLK = 0; // eCAP4 clock off
SysCtrlRegs.PCLKCR1.bit.ECAP5ENCLK = 0; // eCAP5 clock off
SysCtrlRegs.PCLKCR1.bit.ECAP6ENCLK = 0; // eCAP6 clock off
SysCtrlRegs.PCLKCR1.bit.ECAP1ENCLK = 0; // eCAP1 clock off
SysCtrlRegs.PCLKCR1.bit.ECAP2ENCLK = 0; // eCAP2 clock off
SysCtrlRegs.PCLKCR1.bit.EQEP1ENCLK = 0; // eQEP1 clock off
SysCtrlRegs.PCLKCR1.bit.EQEP2ENCLK = 0; // eQEP2 clock off
SysCtrlRegs.PCLKCR3.bit.CPUTIMER0ENCLK = 1; // CPU Timer 0 clock on
SysCtrlRegs.PCLKCR3.bit.CPUTIMER1ENCLK = 0; // CPU Timer 1 clock off
SysCtrlRegs.PCLKCR3.bit.CPUTIMER2ENCLK = 0; // CPU Timer 2 clock off
SysCtrlRegs.PCLKCR3.bit.DMAENCLK = 1; // DMA Clock clock on
SysCtrlRegs.PCLKCR3.bit.GPIOINENCLK = 0; // GPIO input clock clock off
SysCtrlRegs.PCLKCR3.bit.XINTFENCLK = 1; // XTIMCLK clock on
// Set XCLKOUT to SYSCLKOUT ratio to 1:1
XintfRegs.XINTCNF2.bit.XTIMCLK = 0; // XTIMCLK = SYSCLKOUT
XintfRegs.XINTCNF2.bit.CLKMODE = 0; // XCLKOUT = XTIMCLK
XintfRegs.XINTCNF2.bit.CLKOFF = 0; // Enable XCLKOUT
EDIS;
}
It seems that whenever I make a change to the XintfRegs.XINTCNF2 register the pin no longer outputs the clockout.
