Other Parts Discussed in Thread: C2000WARE
Dear Experts,
We are developing some new code elements for the ARM Cortex M4 (CM) core, where we are attempting to do float operations on the core. When the CM core project is built with floating point support enabled (FPv4SPD16) the core executes correctly until it hits floating point instructions (e.g. VLDR S0, [R2, #4]), where a hardfault occurs and the default fault ISR is called. Through Investigating the issue, the no coprocessor usage flag [NOCP] is set in the CFSR register, which appears to be escalated to a forced hard fault (Forced bit is set in the HardFault Status Register (HFSR)).
Attempting to verify if the CM core implementation has the FPU block or not through documentation gives no clear indication, however given the lack on mention of the unit in any of the documentation, this strongly suggests it is not implemented. Additionally when attempting to write to the location of the Coprocessor Access control register [CPACR], listed under 7-2 of the Cortex M4 User Manual, as located at 0xE000ED88, the value is not retained which also may suggest that this is indeed not implemented.
Does the Cortex M4 Implementation in the Target part (TMS320F28384D) have the floating point unit implemented? If so, is there any examples available for configuring the unit so we may support FP operations on the CM core.
Additionally, when checking for errors, the MMFAR and BFAR registers have the address 0xE000EDF8 in both, regardless of the configuration above, which is in the same region as the missing CPACR register. I also verified this on example firmware in the C2000ware demos for the CM Core IPC Communications (ipc_ex1_basic_cm). Is this related to the issues I am seeing on the FPU? Is this normal behaviour?
Thanks for any help you may be able to provide.
Best Regards,
Scott.
