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TMS320F28075: Peripheral regster access speed

Part Number: TMS320F28075

Dear Champs,

I am asking this for our customer. 

Now customer is under tuning the code optimization for program execution efficiency in the ISR.

So they want to know whether TI can provide the F28075 peripheral register access speed, especial in ADC and PWM.

so they want to clarify below question.

 

How is the fastest speed if we direct access c2000 peripheral registers from C28/CLA?

Regards,

Daniel

  • Hello Daniel,

    The expert is currently on travel, so responses may be delayed.

    Best regards,

    Omer Amir

  • Daniel,

        I am not sure exactly what the customer wants to know. The speed at which the 28x CPU (or CLA) accesses a peripheral register is fixed (and such accesses likely happen at zero wait-states). I don't understand how knowing this value would help optimize the code. If code optimization provided the compiler is insufficient, customer can look at C-callable assembly. Over time, compilers have improved to the extent where the performance gap of C code compared to assembly has narrowed.

  • Daniel,

                  Our compiler expert provided the following feedback:

    "...The compiler has no direct role here.  If a variable is associated with a peripheral, you need to mark it volatile.  That means the compiler never keeps it in a register, and always accesses it with the same pattern as the C source.  Thus, there is no opportunity for optimization...."

  • Hi Daniel,

    In general the C2000 architecture has low latency peripheral accesses. ADC reads take 1 cycle and PWM writes 2-3 cycles. There will be few additional cycles for moving address of the peripheral and data into CPU registers. They can benchmark the reads and writes in their code to get the exact number.

    Hope this helps.

    Thanks,

    Ashwini