• State TI Thinks Resolved
  • Locked Locked
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 82 subscribers
  • Views 192 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

PMP23126: Startup at closedloop control

Gokhan G.
Intellectual 765 points
Part Number: PMP23126


Hi,

I'm reviewing PMP23126 software.

I have questions about softstart at closedloop. The softstart is written at interrupt service routine and there is some lines checking 5% Vref, 10% Vref and others. 

1) In below lines for startup, why is there need to load higher valued deadband to PWM1? Could you please explain idea behind it?

        if(PSFB_vLVBus_Volts < (PSFB_VOUT_TYPICAL_VOLTS*0.05f)) // 5% Vref
        {

            if (PSFB_cntlMax < PSFB_IREF_Max_PU)
            {
                PSFB_cntlMax = PSFB_cntlMax + PSFB_IREF_Max_STEP_PU;
                PSFB_cntlMin = PSFB_cntlMin + PSFB_IREF_Min_STEP_PU;
                EPWM_setFallingEdgeDelayCount(PSFB_FB_PWM1_BASE, initial_db);
                EPWM_setRisingEdgeDelayCount(PSFB_FB_PWM1_BASE, initial_db);
            }

2) What is the purpose of Frequency Folding?  Why is there need to change PSFB_FB_PWM_PERIOD_TICKS? Could you please explain idea behind it?

    // Frequency folding
    if(PSFB_freq_fold_enable == 1)
    {
        .....
 

  • 0
    TI__Mastermind 27145 points

    Hi Gokhan,

    1. PWM1 corresponds to the primary side pair that experiences the passive to active transition within the PSFB switching cycle and experiences more hard switching compared to the active to passive transition within the switching cycle. Too small of a dead time led to a large current spike that would trip OCP during startup. The deadtime is allowed to adjust after startup is complete.

    2. At very light load, the MCU reduces the switching frequency in order to deliver a lower amount of power to the output while maintaining a minimum overlap time between Leg1 and Leg2 of the primary side. This enables the converter to achieve lower effective duty cycle to maintain regulation of the 12V output at very light load. PSFB_FB_PWM_PERIOD_TICKS is updated to facilitate lowering the switching frequency at light load. 

    Best Regards,

    Ben Lough