TMS320F28377D: Help SDFM timing for getting new data (AMC1303M0510) and configuration

Arun Kumar

Part Number: TMS320F28377D
Other Parts Discussed in Thread: SYSCONFIG

Hi Experts ,

I have configured the SDFM module to use sin3 filter with a control loop OCR of 58, which would give me approximately 12 bits(ENOB)

Here is the SDFM setup:

void HAL_setupSDFM(HAL_MTR_Handle handle)
{
    HAL_MTR_Obj *obj = (HAL_MTR_Obj*) handle;
    //
    // Input Control Unit
    //
    // Configure Input Control Unit: Modulator Clock rate = Modulator data rate
    //
    SDFM_setupModulatorClock(obj->sdfmHandle, SDFM_FILTER_1, SDFM_MODULATOR_CLK_EQUAL_DATA_RATE);
    SDFM_setupModulatorClock(obj->sdfmHandle, SDFM_FILTER_2, SDFM_MODULATOR_CLK_EQUAL_DATA_RATE);
    SDFM_setupModulatorClock(obj->sdfmHandle, SDFM_FILTER_3, SDFM_MODULATOR_CLK_EQUAL_DATA_RATE);

    //
    // Configure comparator filter settings(Not used)
    //
    SDFM_configComparator(obj->sdfmHandle, (SDFM_FILTER_1 | SDFM_FILTER_SINC_1 | SDFM_SET_OSR(32)), SDFM_THRESHOLD(32767,0));
    SDFM_configComparator(obj->sdfmHandle, (SDFM_FILTER_2 | SDFM_FILTER_SINC_1 | SDFM_SET_OSR(32)), SDFM_THRESHOLD(32767,0));
    SDFM_configComparator(obj->sdfmHandle, (SDFM_FILTER_3 | SDFM_FILTER_SINC_1 | SDFM_SET_OSR(32)), SDFM_THRESHOLD(32767,0));

    //
    // Configure data filter settings(Page 1814 of Tech Manual)
    //
    SDFM_configDataFilter(obj->sdfmHandle, (SDFM_FILTER_1 | SDFM_FILTER_SINC_3 | SDFM_SET_OSR(58)), (SDFM_FILTER_ENABLE | SDFM_DATA_FORMAT_16_BIT | SDFM_SHIFT_VALUE(3)));
    SDFM_configDataFilter(obj->sdfmHandle, (SDFM_FILTER_2 | SDFM_FILTER_SINC_3 | SDFM_SET_OSR(58)), (SDFM_FILTER_ENABLE | SDFM_DATA_FORMAT_16_BIT | SDFM_SHIFT_VALUE(3)));
    SDFM_configDataFilter(obj->sdfmHandle, (SDFM_FILTER_3 | SDFM_FILTER_SINC_3 | SDFM_SET_OSR(58)), (SDFM_FILTER_ENABLE | SDFM_DATA_FORMAT_16_BIT | SDFM_SHIFT_VALUE(3)));

    //
    // Configure SDSYNC (Filter reset from PWM)
    //
    SDFM_disableExternalReset(obj->sdfmHandle, SDFM_FILTER_1);
    SDFM_disableExternalReset(obj->sdfmHandle, SDFM_FILTER_2);
    SDFM_disableExternalReset(obj->sdfmHandle, SDFM_FILTER_3);

    SDFM_enableInterrupt(obj->sdfmHandle, SDFM_FILTER_1, SDFM_DATA_FILTER_ACKNOWLEDGE_INTERRUPT);
    SDFM_enableInterrupt(obj->sdfmHandle, SDFM_FILTER_2, SDFM_DATA_FILTER_ACKNOWLEDGE_INTERRUPT);
    SDFM_enableInterrupt(obj->sdfmHandle, SDFM_FILTER_3, SDFM_DATA_FILTER_ACKNOWLEDGE_INTERRUPT);

    SDFM_disableInterrupt(obj->sdfmHandle, SDFM_FILTER_1,
                (SDFM_HIGH_LEVEL_THRESHOLD_INTERRUPT |
                 SDFM_LOW_LEVEL_THRESHOLD_INTERRUPT |
                 SDFM_MODULATOR_FAILURE_INTERRUPT));
    SDFM_disableInterrupt(obj->sdfmHandle, SDFM_FILTER_2,
                    (SDFM_HIGH_LEVEL_THRESHOLD_INTERRUPT |
                     SDFM_LOW_LEVEL_THRESHOLD_INTERRUPT |
                     SDFM_MODULATOR_FAILURE_INTERRUPT));
    SDFM_disableInterrupt(obj->sdfmHandle, SDFM_FILTER_3,
                    (SDFM_HIGH_LEVEL_THRESHOLD_INTERRUPT |
                     SDFM_LOW_LEVEL_THRESHOLD_INTERRUPT |
                     SDFM_MODULATOR_FAILURE_INTERRUPT));

    //
    // Enable master interrupt so that any of the filter interrupts can trigger
    // by SDFM interrupt to CPU
    // Note: This is enabled in PWM ISR, so that phase currents are ready once every PWM cycle
    //
    SDFM_disableMasterFilter(obj->sdfmHandle);
}

I found this useful excel tool:

In the excel it says that filter settling time would be 17.4 microseconds.

Looking at the MCU's technical reference manual, in the AFx event section:

So does that mean that when ever the master interrupt is enabled(SDCTL.MIE = 1), it will take 17.4 microseconds for the AFx event to occur?

Secondly could you confirm that all the four filter channels of the SDFM module work parallelly? Do I need to check the status of all AFx events or can I get away with just polling any one AFx event?

over 3 years ago

0 Arun Kumar over 3 years ago

Expert 1030 points

One more followup question , even though i had configured the SDFM module for an ENOB of 12 bits, i still see that the data exceeds max value of 4096?

I have shifted but bits by 3:

SDFM_configDataFilter(obj->sdfmHandle, (SDFM_FILTER_1 | SDFM_FILTER_SINC_3 | SDFM_SET_OSR(58)), (SDFM_FILTER_ENABLE | SDFM_DATA_FORMAT_16_BIT | SDFM_SHIFT_VALUE(3)));

Can you clarify as to what can be the maximum value?

0 Kevin Allen18 over 3 years ago in reply to Arun Kumar

TI__Mastermind 45606 points

Hi Ak,

Arun Kumar said:
So does that mean that when ever the master interrupt is enabled(SDCTL.MIE = 1), it will take 17.4 microseconds for the AFx event to occur?

I'll need to verify and get back to you when AFx gets set.

Arun Kumar said:
Secondly could you confirm that all the four filter channels of the SDFM module work parallelly? Do I need to check the status of all AFx events or can I get away with just polling any one AFx event?

The AMC1303 generates its own clock to the C2000'sd SDFM input. I don't think multiple devices could stay synchronized with each other over time, therefore you should check all AFx events. There are other AMCx devices that accept a clock input, just an FYI.

Also, I will mention that AMC1303Mx timing requirements do not exactly meet C2000 SDFM timing requirements by default. We have found that inverting the SDFM clock input to the C2000 using the GPIO inversion feature (GPxINV) solves this issue. I can send you more info on this if you'd like.

Arun Kumar said:
One more followup question , even though i had configured the SDFM module for an ENOB of 12 bits, i still see that the data exceeds max value of 4096?

What value range are you seeing instead?

Best,

Kevin

0 Arun Kumar over 3 years ago in reply to Kevin Allen18

Expert 1030 points

Kevin Allen18 said:
Also, I will mention that AMC1303Mx timing requirements do not exactly meet C2000 SDFM timing requirements by default. We have found that inverting the SDFM clock input to the C2000 using the GPIO inversion feature (GPxINV) solves this issue. I can send you more info on this if you'd like.

I did not know this, will try inverting and checking it.

Kevin Allen18 said:
What value range are you seeing instead?

About +- 24000 count.

I am reading the data like this:

#define READ_CURRENT_SDFM()														\
/* Set SDFM output data format*/                                               \
   SDFM_setOutputDataFormat(M2_SDFM_BASE, SDFM_FILTER_1, SDFM_DATA_FORMAT_16_BIT); \
   SDFM_setOutputDataFormat(M2_SDFM_BASE, SDFM_FILTER_2, SDFM_DATA_FORMAT_16_BIT); \
   SDFM_setOutputDataFormat(M2_SDFM_BASE, SDFM_FILTER_3, SDFM_DATA_FORMAT_16_BIT); \
/* Enable SDFM Master Interrupt*/                                              \
   SDFM_enableMasterFilter(M2_SDFM_BASE);                                     \
/* Wait for SDFM to complete acquiring data*/                                  \
   while(pMotor->SdfmIntFlag->bit.AF1 == 1);                                  \
   while(pMotor->SdfmIntFlag->bit.AF2 == 1);                                  \
   while(pMotor->SdfmIntFlag->bit.AF3 == 1);                                  \
/* Store the data in appropriate variables*/                                   \
   AMC1303Vars[1].rawfilter1Result = (int16_t) (SDFM_getFilterData(M2_SDFM_BASE, SDFM_FILTER_1) >> 16U);        \
   AMC1303Vars[1].rawfilter2Result = (int16_t) (SDFM_getFilterData(M2_SDFM_BASE, SDFM_FILTER_2) >> 16U);        \
   AMC1303Vars[1].rawfilter3Result = (int16_t) (SDFM_getFilterData(M2_SDFM_BASE, SDFM_FILTER_3) >> 16U);        \
/*Clear the interrupt.*/                                                       \
   SDFM_clearInterruptFlag(M2_SDFM_BASE, SDFM_MASTER_INTERRUPT_FLAG | 0xFFFF);                                  \
   Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP5);                             \

And this is the count data that is captured from the data logger(The orange color line graph):

+1 Kevin Allen18 over 3 years ago in reply to Arun Kumar

TI__Mastermind 45606 points

Hi Ak,

Arun Kumar said:
So does that mean that when ever the master interrupt is enabled(SDCTL.MIE = 1), it will take 17.4 microseconds for the AFx event to occur?

AFx event should get set at the Data rate of the Sinc filter. so 17.4 / 3 in your case of Sinc3.

Arun Kumar said:
About +- 24000 count.

I am reading the data like this:

This is the correct range assuming you're using 16-bit representation. We have a tool in the SDFM Sysconfig module for calculating these kind of filter data outputs. Please see below for your case:

Best,

Kevin

0 Arun Kumar over 3 years ago in reply to Kevin Allen18

Expert 1030 points

Thanks Kevin, the sysconfig tool was helpfull. I was under the impression that the SDFM data will be automatically aligned to the the ENOB value of 12 bits.

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TMS320F28377D: Help SDFM timing for getting new data (AMC1303M0510) and configuration