TMS320F28388D: BissC - CLB Clock setting to 100/150Mhz

Hello Dorion,

Dorion Carr said:

1. Is there a way to change the CLB clock to run slower and not be reliant on the system clock or PWM?

You can use the SysCtl_setCLBClk function to change the CLBCLKDIV and TILECLKDIV as shown in the CLB Clock section of the CLB chapter in the device reference manual. Please note that to use the CLB-specific clock dividers, the CLB needs to be configured for ASYNC mode (it will be deriving its clock from the AUXPLL rather than the SYSCLK). You can find the SysCtl_setCLBClk function and the associated enumerators in the sysctl.h header file.

Dorion Carr said:

2. If the CLB clock is running at 200Mhz, I set the pipeline value in the register but no effect. Could this be causing BissC errors.

I assume you're talking about the pipeline mode, not the input pipeline filter. The pipeline mode is what enables the CLB to run up to 150 MHz, but it's not used for any frequency beyond that from what I understand. I don't know if this would cause the errors you're seeing, I'll let the BissC expert answer that.

Best regards,

Omer Amir

Dorion,

An option is to use the AUXPLL to clock the CLB. 

Omer Amir said:

If the CLB clock is running at 200Mhz, I set the pipeline value in the register but no effect. Could this be causing BissC errors.

The CLB is not designed to run at 200MHz on this device. 

Omer Thanks. We were able to use the AuxPLL

Lori,

  Could we get BISS C errors if we were running at 200MhZ? I would assume the CLB behavior is unpredictable.

Dorion

Correct - the CLB behavior is not defined if you are running at 200MHz. Therefore, the impact on BiSS is unpredictable.

OK. Next question.

If my clock is running at 200Mhz my AuxPLL is now making the CLB run at 100Mhz.

What should my BissC frequency clock be? Keep in mind my SysCtl_setLowSpeedClock is SYSCTL_LSPCLK_PRESCAE_1 and my

#define DEVICE_AUXCLK_FREQ          ((DEVICE_OSCSRC_FREQ * 100) / (5 * 1 * 1))

and my

// 20MHz XTAL on controlCARD. For use with SysCtl_getClock() and
// SysCtl_getAuxClock().
//
#define DEVICE_OSCSRC_FREQ          25000000U

I have set my frequency clock to 25 is that correct?

These changes seem to have helped with the BissC CRC errors but we are still getting some.

We have been using the example for BissC sent to us.

Dorion

I have set my PM_bissc_setFreq(25)

Also, for SPI since it is a slave what is generating the clock for the SPI interface is that the CLB?

Yes, the CLB generates the SPI clock. 

I just realized you are trying to run our BiSS-C library on F28388x. The library was developed for the F2837xD and I don't think it will directly port to F28388x without modification.  Unfortunately we do not have the source in our collateral. 

Lori,

  So I was able to load the sysconfig into our project and it generated the CLB code. What specificly was developed for the F2837xD?

  How can we get something that was for the F28388x? We kindof need it.

Dorion