• State
  • Locked Locked
  • Replies 1 reply
  • Subscribers 82 subscribers
  • Views 604 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS320F28388D: State Machine Structure for Including ADC/DMA/ETH/SCI/PLL/PWM Interrupt Application

ozn o.
Intellectual 280 points
Part Number: TMS320F28388D


Hello,

I want to develop software using F28388D.
In this software I will use ADC, DMA, Ethernet, SCI, Center Aligned Deadband PWM and PLL.

With ADC and DMA I want to read 4 different sensor data (current and voltage every 20 microseconds, 2 different temperature measurements every one second).

Since I need to generate a continuous signal instantaneously, the PWM (50 kHz) will generate an interrupt on the rising edge every 20 microseconds and within this interrupt function I will do a trigonometric calculation that will take about 1.5 microseconds. (This calculated value will be the next PWM duty value in the continuously generated signal. The PWM interrupt should be a priority interrupt. But this priority should not negatively affect the data of units such as ADC, ETH, PLL, SCI).

I want to clamp the sine current and voltage I produce using PWM with PLL and measure the phase difference between current and voltage.

There will be PC communication with Ethernet. ADC data and some error information will be sent to the PC. In some cases user parameters will be sent from the PC to the MCU.

I need your comments and support for this software.

If everything except the PWM interrupt in the state machine works in polling mode, will continuous PWM interrupts cause incorrect data in ADC, ETH, SCI read and write states? How should the system work here?

How can I build the state machine structure with a single CPU?

Would it be advantageous to use dual CPU? For example, would it be better if PWM and PLL are in CPU1, ADC, ETH, SCI are in CPU2? (I have not developed with Dual CPU, an additional learning and understanding process will be required to develop the software).

Thank you.

  • 0
    TI__Mastermind 28230 points

    Hi blackmatter,

    For which peripherals do you expect to use an interrupt? Using two CPUs will certainly reduce the risk of conflicting interrupts, however I am not sure if this is necessary depending on the length of each of your ISRs. I would suggest developing your system on a single CPU but taking note of the execution time of each of your ISRs. If it turns out there are too many conflicting interrupts in your system, it's feasible to port your code from a single CPU project to a dual-core project.

    A common edge-case with PWM when many interrupts are present is if a PWM interrupt is fired while another interrupt is being serviced, resulting in the PWM ISR being delayed. If you set up your PWM ISR in a manner that it must complete within one PWM cycle(for example many PWM settings are being updated within a single cycle), delaying the beginning of the PWM ISR will result in a irregular mix of old and new PWM settings, since many PWM settings are shadow-loaded on PWM TBCTR=0. This will result in un-desired behavior in your PWM outputs that will be difficult to debug if you haven't considered the potential delay of the beginning of the ISR. Not saying dual-core is absolutely necessary, but I would observe the beginning and end of each of your ISRs by toggling GPIOs if you attempt to implement your system on a single core, and check if your PWM interrupt is starting and completing within a single cycle.