TMS320F28379D: tms320f28379d

Based on the logs it seems like TRSTn is pulled low. Can you share the JTAG portion of your schematic? Also, what is the boot mode you are using on the device? 

Hello Gus Martinez,

Thanks for the response,

Sorry for the late reply.

Find the below attached image for JTAG portion of my schematic.

The boot mode we are selecting is FLASH (where Pin 0 = 1 and Pin 1 = 1), find the attached image for boot mode configuration.

Thanks & Regards

K. Aravind,

9848992750,

Sigma Advanced Systems. 

Thanks for providing the schematic information. It looks like it follows the datasheet recommendation for the JTAG signals. I didn't see anything obviously wrong. You could try to observe the TRSTn signal using a scope and verify that the VIH/VIL levels are being met.

Another thing you can try is to run the "test connection" feature from the target configuration file in CCS. There are more details in chapter 5 of the app note below.

https://www.ti.com/lit/an/spracf0b/spracf0b.pdf

Hello Gus Martinez,

        When I open the GPIO 72(BOOT PIN) of the controller, CPU 1 flash is working but CPU 2 flash is not working, 

When it comes to RAM both cores is working, What might be the problem.

I also checked the "test connection" it is getting passed.

Thanks & Regards,

K. Aravind,

Sigma Advanced Systems,

9848992750.

Arvanid,

Thanks for clarifying that the JTAG connection looks good. The issue you are seeing now may be related to the boot flow. I'll see if somebody more familiar with that flow can comment. 

Hello Aravind.

Do you have anything programmed in the DCSM locations? (User OTP). Since you can connect to the debugger, can you please share the dump of that data?

-Kedar