Hello experts,
I have a question regarding the behavior of the ADC SOC control in burst mode.
In my application the ADC converts multiple channels sequentially one after another in burst mode. The SOC trigger is generated in an ePWM module configured in up-down count mode. The SOC is generated when TBCTR = zero and TBCTR = period. So far, no problem.
I want to synchronize the ePWM module via the FSI. The synchronization should set the TBCTR to zero. Because of the synchronization jitter and clock drift, the TBCTR = zero event could occur twice within a few SYSCLK cycles, triggering two SOC pulses.
What happens if two SOC pulses are generated in a short period of time so that the first conversion of the burst is still in progress? Is the second SOC pulse ignored? Or does it trigger a next burst right after the current burst is completed?
Best regards,
Stefan
