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TMS320F28075: SPI transmission by DMA scheduling

Kenley
Intellectual 1945 points

Part Number: TMS320F28075

Hi team,

My customer has a question for SPI transmission by DMA.

Currently, they are using SPI data transmission/reception is performed by DMA.
Is it possible to allocate Global shared RAM GSx RAM in the same section?
In this case, I think there would be an access conflict. At that time, will the order of access will be round robin schedule?
It means there will be some access waiting, and will write or read sequentially. Is it correct?

Thank you in advance.

Best regards,

Kenley

  • 0
    TI__Guru* 84940 points

    Kenley,

    The DMA and CPU will cycle back and forth if there are accesses to the same memory region.  Given the speed of the SPI transmission(slow) compared to the CPU(fast); I would expect these disruptions to be minimal, and not resulting in any SPI data loss.  The only way I can think that the CPU would keep the bus occupied is if there was some type of mass copy of data, and the compiler used a repeatable ASM instruction to do this.  Customer can comment on how the CPU is using the GSx RAM, but I think this wouldn't be likely scenario.

    Arbitration is mentioned in the TRM in the DMA chapter.

    Best,

    Matthew