TMDSSOLARUINVKIT: Support for two PV panels

I know that on schematic there are two fly-back MPPT DC/DC converters but how about from software side?

PWM4 to control second fly-back MPPT DC/DC converter and IPV_2_SEN (ADC-A3) for measuring current of second panel? Am I right?

In other words.. you mean that in the TMDSSOLARUINVKIT software there is everything to have a fully support of two PV panels?

OK, then, I will try it and let you know. Thanks Shamim Choudhury.

Hi Shamim Choudhury I checked the software for support two PV panels. Unfortunately, I did not find any entries for their support so I started to create support for the second PV panel.
Please check my configuration for initialization of PWM, ADC, COMP and protection mechanism.
I am still working on the logic so any advice from your side will be appreciated.

Here is my configuration for handle second PV panel. Measuring IPV2 happends on ADC_B4 and VPV2 is on ADC_B3. PWM4 is used for controling second flyback converter. COMP2 is used for PWM4 protection mechanism.

GPIO setup in SolarMicroInv-DevInit_F2803x.c file:

GpioCtrlRegs.GPAMUX1.bit.GPIO7   = 1;        // 0=GPIO, 1=EPWM4B, 2=SCIRX-A, 3=Resv

Initialisation

// PWM4 init.
PWM_1ch_UpDwnCnt_CNF(4, (CPU_FREQ / (FLYBACK_FREQ)), 0, (CPU_FREQ / (FLYBACK_FREQ * 2)) - 2);

// Add the dead band configuration for PWM4.
EALLOW;
EPwm4Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;  // rising delay on 1A & falling delay on 1B
EPwm4Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;       // active high complementary mode (EPWMxA is inverted)
EPwm4Regs.DBCTL.bit.IN_MODE = DBA_ALL;          // 1A for rising & falling
EPwm4Regs.DBRED = FLYBACK_DEADBAND_RED;         // delay at rising edge
EPwm4Regs.DBFED = FLYBACK_DEADBAND_FED;         // delay at falling edge
EDIS;

// ADC config.
#define IPV2_FB     AdcResult.ADCRESULT10
#define VPV2_FB     AdcResult.ADCRESULT11
	
// EPWM 4 SOC signals.
ChSel[10] = 12;             // B4 - IPV2
ChSel[11] = 10;             // B3 - VPV2

// Select Trigger Event.
// EPWM 4.
TrigSel[10] = ADCTRIG_EPWM4_SOCA;
TrigSel[11] = ADCTRIG_EPWM4_SOCA;

// Configure the PWM to issue appropriate start of conversion for the ADC.
// DC-DC Flyback.
EPwm4Regs.ETSEL.bit.SOCAEN = 1;             // enable SOC on A group.
EPwm4Regs.ETSEL.bit.SOCASEL = ET_CTRD_CMPB; // select SOC from counter at ctr = 0
EPwm4Regs.ETPS.bit.SOCAPRD = ET_1ST;        // generate pulse on 1st even
EPwm4Regs.ETSEL.bit.SOCAEN = 1;             // enable SOC on A group
EPwm4Regs.CMPB = 12;

Protection Mechanisms:

// Cycle by cycle interrupt for CPU halt trip.
EPwm4Regs.TZSEL.bit.CBC6    = 0x1;

// Adding one shot trip for over current of the flyback2 stage but avoid the <1% duty condition using blanking.
//------------------------------------------------
// First enable the COMP2.
Comp2Regs.COMPCTL.bit.COMPDACEN             = 0x1;
Comp2Regs.COMPCTL.bit.SYNCSEL               = 0x0;  // asynchronous version of the COMP signal is passed to the EPWM/GPIO module
Comp2Regs.COMPCTL.bit.CMPINV                = 0x0;  // output of the comparator is passed directly
Comp2Regs.COMPCTL.bit.COMPSOURCE            = 0x0;  // inverting input of the comparator is connected to the internal DAC
Comp2Regs.DACVAL.bit.DACVAL                 = 700;  // set DAC input to peak trip point ~10 Amps, full scale is 15Amps
AdcRegs.COMPHYSTCTL.bit.COMP2_HYST_DISABLE  = 0x1;

// Select COMP2 as one shot trip.
EPwm4Regs.DCTRIPSEL.bit.DCAHCOMPSEL         = DC_COMP2OUT;
EPwm4Regs.TZDCSEL.bit.DCAEVT1               = TZ_DCAH_HI;
EPwm4Regs.DCACTL.bit.EVT1SRCSEL             = DC_EVT_FLT;
EPwm4Regs.DCACTL.bit.EVT1FRCSYNCSEL         = DC_EVT_ASYNC;
EPwm4Regs.TZSEL.bit.DCAEVT1                 = 0x1;
//------------------------------------------------

// Add blanking to avoid conditions where the over current trip generates <1% duty cycle.
//------------------------------------------------
EPwm4Regs.DCFCTL.bit.BLANKE     = DC_BLANK_ENABLE;  // blanking window is enabled
EPwm4Regs.DCFCTL.bit.BLANKINV   = DC_BLANK_NOTINV;  // blanking window is not inverted
EPwm4Regs.DCFCTL.bit.SRCSEL     = DC_SRC_DCAEVT1;   // DCAEVT1
EPwm4Regs.DCFCTL.bit.PULSESEL   = DC_PULSESEL_PRD;  // apply offset from TBCTR=TBPRD
EPwm4Regs.DCFOFFSET             = 59;
EPwm4Regs.DCFWINDOW             = 255;
//------------------------------------------------

// What do we want the OST/CBC events to do?
// TZA events can force EPWMxA.
// TZB events can force EPWMxB.
//------------------------------------------------
EPwm4Regs.TZCTL.bit.TZA         = TZ_FORCE_LO;      // EPWMxA will go low
EPwm4Regs.TZCTL.bit.TZB         = TZ_FORCE_LO;      // EPWMxB will go low

// Clear any spurious trips.
EPwm4Regs.TZCLR.bit.OST         = 1;

// Force a trip event on all the PWM modules for safety.
EPwm4Regs.TZFRC.bit.OST         = 0x1;

Hi Shamim Choudhury. Yes, I working on logic right now. My PWM4 is based on PWM3 settings but I have a question.

You said:

Shamim Choudhury said:

Then your PWM4 code for 2nd PV will be similar except that it will have a half PWM period phase shift with PWM3.

Why? Since second PV panel is connected to the second flyback DC-DC converter?

Shamim Choudhury during GPIO07 setup which I want to use for EPWM4B. I have found these settings:

//  GPIO-07 - PIN FUNCTION = OPRLY
	GpioCtrlRegs.GPAMUX1.bit.GPIO7 = 0;		// 0=GPIO,  1=EPWM4B,  2=SCIRX-A,  3=Resv
	GpioCtrlRegs.GPADIR.bit.GPIO7 = 1;		// 1=OUTput,  0=INput
	GpioDataRegs.GPACLEAR.bit.GPIO7 = 1;	// uncomment if --> Set Low initially
//	GpioDataRegs.GPASET.bit.GPIO7 = 1;		// uncomment if --> Set High initially

and wondering for which purposes GPIO07 is used in code.

GPIO7 is for output relay control.

Thanks for decoding this shortcut but relay is not connected to the GPIO07 but GPIO22. I couldn't find the use of GPIO07 which I want to use for PWM but when I saw "OPRLY" thought I'd ask.