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TMS320F28P650DK: Time-Base Counter Synchronization: How to generate EPWMxSyncOut pulse

Ettore Marroni
Prodigy 200 points

Part Number: TMS320F28P650DK

Hi support team, 

first of all, I'm apologizing but I still need your support.

I'm trying to synchronize some Epwm modules, with Epwm1 as the master module that provides "sync output pulse" to the slave Epwm modules.

The next picture shows the synchronization chain.

 

Now I'm going to describe my reasoning applied to 28P65X.

Figure  22-7 shows the scheme, and the register TBCTL with the "Sync output options": please refer to the red square on the picture.

Looking the fields of TBCTL register, I'm not able to find the "Sync output options": please refer to the next picture.

Further, comparing TBCTL register belonging to 28P65X with the one belonging to 2837xD, the field "SYNCOSEL" it is reserved on the new chip.

So at the end, can you help me to generate a sync output pulse when 

CTR = zero: Time-base counter equal to zero (TBCTR = 0x00)

on the master Epwm module ?

Thank you.

Best regards,

Ettore

  • +1
    TI__Genius 11076 points

    Hello Ettore,

    Take a glance at the following tables from the device TRM:

     

    So, on the primary ePWM, select EPWMSYNCOUTEN[ZEROEN] = 0x1 to propagate CTR=ZRO to the SYNCO signal out of the ePWM.

    Note the AND gates in the image you provided- EPWMSYNCOUTEN gates whether or not the compare events, such as CTR=ZRO as discussed, are propagated to SYNCO. That said, I'll make a note to the team that the inclusion of TBCTL in grey there is confusing and, I believe, unnecessary.

    Hope that helps,
    Jason Osborn