ASM control with TMS320F28335

Hello,

this is me again, with another question about my problem of realizing a control for an ASM.

The thing is, it's really hard for me to understand these things, and that may be the reason why I do not understand some application notes and examples.

afaiu, I need two inputs for the currents, sampled at 40kHz, and 6 PWM-outputs running at 20kHz in up/down-mode – 3 in active-low mode and 3 in active high for the VSI. Apart from that, to sense the mechanical speed, I'ññ use an encoder connected to the QEP-inputs.

The more often I read manuals and transparencies I find on the net, the dizzier I get because of the bits I have to fit into registers.

Unfortunately I will not have a TMS320F28335 at hand until september, but I am trying to develop my code as I want to finish my Master-thesis.

Let me start with how I understand the ADC and want to make it work.

I understand I have to set some bits, from 15 to 0 in the ADCTRL1-register.

These would be: [1 bit reserved ???]100[4 bit prescaling][1bit prescaler /2]110[4 bit reserved ???]

Apart from the fact that I do not know what to do with the reserved bits, I guess they should be laeft as they are, I want to:

• reserved bit

• 1: reset the adc

• 00: apply mode 0 (free run)

• [4 bit prescaling]apply a prescaling based on whatever clock

• another prescaling division.... well I hope to be able to reach 40kHz with that and the bits before

• 1: continuous run

• 1: seq pointer resets to initial state after end state (what ever that means – sounds more “normal” to me)

• 0: dual mode, so that adcina0 and adcinb0 are read simultaneously

• 4 reserved bits

Then I will have to set up ADCTRL2:

• won't care about msb (dual mode)

• 1: I will reset on init (I guess it is better)

• 1: every conversion when I call the result in main?

• Reserved bit

• 1: interrupt enable, I guess

• 0 or 1: now I read 0: “interrupt every EOS” 1: “interrupt every other EOS”

• reserved

• 0 or 1: cannot be started by EVA-trigger or can be started by EVA trigger ??!??

• lower byte similar to upper byte

ADCTRL3

• upper byte reserved

• then there are 3 bits I do not understand

• and another prescaler, why ever

• 1: simultaneous sampling

MAXCONV – don't know what to do with it.

Once this works by miracle, as I still do not know the correct syntaxes (minor problem, I hope), I will be able to read the result as unsigned integer like, after an offset is applied to the inputs.

value1=AdcRegs..ADCRESULT0 >> 4; (12 Bit shifted right)

value2=AdcRegs..ADCRESULT8 >> 4; (12 Bit shifted right)

And that is what I need in 40kHz – in the examples I do not see how it is realized only by setting periods in the registers. There must be an extra timer somewhere else, as all the control cannot work faster than that.

After this, I would transform to Park, which has to be easier than I see in some example functions by TI, but I might have to respect iq-format.

To generate the quadrature current reference, I will have to setup the QEP-inputs. I only found app notes and examples for PMSM, so the demonstrated utilization of QEP I found is not well suited for me as theta is calculated using QEP, but on ASM I will have to estimate it by the currents, which works quite well in powersim.

I think CAPCONA would have to be configured like this:

• 0: reset

• 11: enable for QEP

• 0 or 1: unit 3 control?!?!?

• reserved

• 11: timer 1

• 0: no action

• 111111: detection of both edges on all inputs (why not?)

• 2 reserved

CAPFIFOA

• I guess I will read bits 13...8 to know when there is an entry

• how do I access the result?

When it comes to PWM, as I need 6 outputs for motor control, I really do not know how to configure the timer. I'd try as follows on GPTCONA

As the msb from 15 to 11 are reserved or read only, this time I will begin with 10:

• 0000: no event starts ADC – I will explain a trick I imagine and understand better

• 1: enable outputs

• 2 bits reserved

• 0101: outputs active low – not knowing which pins will be affected

Now my problem is that I do not understand how to make the B-outputs of same index work on active high, negating the corresponding A-output. If it were the timer-2-outputs, how should I sincronize?

If I manage to make it run on on 20kHz in continuous up/down, shouldn´t it be possible to call an AD-conversion everytime the count-direction changes, so it would be sincronized?

The timer/counter is 16 bit, so I guess, 100% corresponds 65535 and I will have to multiply all control coefficients (Kp and Ki) with this dimension. It just makes me a bit dizzy thinking of having to convert to IQ AND multiplying later – is this thought correct?

When it comes to T1CON, I would set:

• 1x: free run

• 1 reserved

• 01: continuous up/down

• XXX: still have to figure out how it is calculated, maybe 111and THEN TxPR=29, but I still did not figure out how to insert this value according to my example

• 1: user timer 1 enable

• 1: timer enable

• 00: clock source internal HSPCLK

• 00 or 01: when counter equels zero/zero or period reg – which is better?

• 1: timer compare operation enable (off course)

• 1: use timer 1 period reg

in EVAIMRA I think I would set all settable bits to 1, as I don't see any problem in having interrupts without routine, and I'd do the same in EVAIMRB.

Maybe I could also trigger an ADC somehow when interrupt “period match” happens – would be the same, but I don't know how to test it.

I see that I can activate a trigger for capture unit inputs 1, 2 and 3 in EVAIMRC.

I see something on my documents that has to be an error, as the register on 0x7431 might be EVAIFRC. If so, I might try looking for an event on one of the capture units and count up until another timer period of higher length has gone by, which means I might need to configure Timer 2 separately, or measure the time between two pulses. The last solution seems like the best, but is it possible to measure frequencies of 100 (pulses) or 200kHz (edges)?

When it comes to use the results of every calculation (control results, decoupling etc.) I need to realize for this, I will finally be able to feed three compare registers every time (not forgetting data conversion) an ADC-conversion has occurred. I am reading that the compare units drive up to two outputs each and that they can be inverted.

So I will propose to set up COMCONA the following way:

• 1: enable

• 01: reload when T1CNT = 0 or T1PR, as sampling data will use double frequency

• 0 or 1: SVM – will I need this “special pattern”? I hope I'll have a sinusoidal modulation

• XX: I do not know when best to reload ACTRA

• 1: I guess, enable would again be best

• 0 or 1: PDPINT status?

• 111: I guess, enabling is best again, but why reserved?

• 2 reserved bits

• XXX: what is tripe?!?!? Is it the inversion of the signal on other ports?!?! If so: 111

Now EXTCONA

• 15-4 reserved

• 1: enable

• 0 or 1: as I still do not know how QEP is to be read, I'd prefer 0

• 0 or 1: I don't know benefits

ACTRA

• 0000: I am not sure about SVM …. I guess, it's best to set all zero for my case

• 000000010101: force low on highest index outputs, active low on first 3 outputs

How do I invert the opposite outputs?

We need a dead time, so we will set up the deadband timer control register, DBTCONA

• 4 bits reserved

• XXXX: need to learn about prescaling and what IGBTs have been used

• 111: I guess, enabling is best again

• XXX: need to learn about prescaler

What I still did not read about, is the PIE-register – what do I have to do there?

Now it's time to deal with the watchdog

WDCR from 7 to 0

• don't care

• 0: watchdog enable

• 101: to enable write access

• 111: to expand time to the maximum (I don't care about clock now)

SCSR from 1 to 0

• X: don't care

• 1: watchdog should not be disabled

In the main procedure I would try this way:

while(1)

{

WDKEY=55h; (however)

if etc.....

… adc, control, decooupling, feed cmpr...

WDKEY=AAh; (however)

}

I hope I did not ask too much, but I am really green with this dsp/uC.

Best regards