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TMS320F28388D: Clock source problem

Rhea Gao
Expert 2580 points
Part Number: TMS320F28388D


Hi，

In the F28388D, Ethercat module and USB module are used, and two active clocks (25M and 6M) are used. The 25M clock is doubled (200M) to provide clock for CPU1,CPU2 and Ethercat module, and the module provides 25M clock for the two PHY chips outside. USB requires an accurate clock, so an auxiliary 6M or 12M clock source is added. The CM core is ready to control Ethercat and USB modules, and the CM core clock is ready to be provided after the auxiliary 6M or 12M clock is doubled (120M).

My question is, since CM uses a 120M clock, Ethercat module uses a 200M clock, and these two parts use different clocks, when CM core controls Ethercat module, will there be any problem when accessing the register of the module because the clock is not synchronized?

Thanks!

  • 0
    TI__Mastermind 45606 points

    Hi Rhea,

    Rhea Gao said:
    My question is, since CM uses a 120M clock, Ethercat module uses a 200M clock, and these two parts use different clocks, when CM core controls Ethercat module, will there be any problem when accessing the register of the module because the clock is not synchronized?

    I didn't find any strict requirement for this in our TI-C2000 documentation, only the below from the TRM section. I did not check Beckhoff's documentation for any requirements like this however, which may be good to do.

    However I will mention that all of our software examples use the same clock source for the ESC and allocated core. I don't believe any testing has been done for different clock sources like you have.

    Best,

    Kevin

  • 0 in reply to Kevin Allen18
    TI__Mastermind 45606 points

    Hi Rhea,

    I have some additional info:

    The registers accessible from the CPU would be in system clock domain, hence those will be synchronised to the PDI clock before being used within the EtherCAT IP. This may require needing some additional delay in software (NOP;) to get values transferred across domains. Such a delay could vary based on frequency of system clock.

    Best,

    Kevin