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TMS320F28379D: DUAL CORE CODE RUN FROM FLASH AFTER RESET OF POWER

Prarambhik Sur
Prodigy 55 points
Part Number: TMS320F28379D
Other Parts Discussed in Thread: C2000WARE

I am trying to use two cores CPU 1 and CPU 2 for my application. My CPU 1 runs all codes for PWMS, ADC and other peripherals. However, I am reading the ADC Result Registers in CPU 2 also and using the same for Short Circuit Protection( which is a time critical task). I want both the codes of CPU 1 and CPU 2 to be run on Flash. It does so when I dump codes in the flash of respective CPU. However, if I reset the power to the DSP  (i.e turning off and then again turning on), I am not getting the expected behavior from CPU2. By expected behavior I mean that in the code for CPU2, I have toggled a GPIO in the main function and set it to high. On resetting when I observe the status of the GPIO in scope, I donot see it to be high.

Note: I have not attached the debugger after reset. My requirement makes it so that I have to dump code one time and on simultaneous runs even after reset it should be running from both cores.

If anybody can assist on this, it would be helpful enough.

 

Thanks,

Prarambhik Sur

(Sr. R&D Engineer, Hind Rectifiers)

  • 0
    TI__Guru* 81500 points

    Prarambhik,

    I would recommend looking at one of the C2000Ware examples for dual core, they are set up to run from flash.  Most likely if you don't see things run standalone the starting point of the code is not mapped to the boot location for flash boot correctly.  I would look at the .cmd files for both of the CPU examples as they will have the correct mapping. 

    The path to one of these examples is here; C:\ti\c2000\C2000Ware_5_00_00_00\driverlib\f2837xd\examples\dual\memcfg\

    Best,

    Matthew

  • 0 in reply to MatthewPate
    Prodigy 55 points

    Hello Matthew,

    I did not find the example that you are currently referring to. It might be because my C2000ware version is lower than 5.0.0.0. I am attaching the screenshot of what I found in the path that you mentioned. Is there any other references for the same.

    TI examples 4.3.0.0

    Thanks,

    Prarambhik

  • 0 in reply to Prarambhik Sur
    TI__Guru* 81500 points

    Prarambhik,

    Thanks for the update, you can use example 1 in the LED folder, I checked and it has similar configuration details.  It looks like there is a build config for FLASH_Standalone for CPU1, I would use that one.  Right now the defaults on both are for RAM targets, just right click on each project and select Build Configurations from the list and change to FLASH.

    Best,

    Matthew

  • 0 in reply to MatthewPate
    Prodigy 55 points

    Hello Matthew,

    Thanks for providing the reference, I will look into it.

    I had a general doubt. I see there are 3 part answers or solutions to code not running in flash for CPU1/CPU2 in power reset. These 3 are as follows as per my understanding:

    1. Using IPC Boot Status. In the ti examples, I have seen that the IPC Boot STatus is called under the if def of STandalone and Flash (pre defined symbols). SO as per my requirement I would be dumping the code once with debugger attached and then remove the debugger and my application should still run in flash even on reset. I donot have a way to dynamically include and remove the STANDALONE option which would be required when I reset my power and both cores still has to run from flash by IPC handshaking. Is my understanding correct and if so, then is there a mechanism to avoid this and still use IPC Boot Status to coordinate between two CPU's?

    2. Configuring BOOT ROM pins. I tried to configure GPIO 19 and 84 as Boot Mode pins(I know its 72 and 84 used, but my application uses GPIO72 for EMIF configuration). I followed some steps. 

                       a. In CPU1, initialized the GPIO as output, pulled them up, and then transferred the ownership to CPU2.

                       b. In CPU2, I set the GPIOs as high, then configure them as Boot MODE pins 0 and 1 using DCSMZ1Regs.Z1_BOOTCTRL, and then put the Key as 0x5A and Boot Mode as 0x0B (boot to flash). This section of DCSM is done under EALLOW and EDIS. 

    After doing this also, when I debug I donot see the DCSM registers getting updated in CPU2 with the values that I gave. I repeated the same thing in CPU1 by just eliminating the transfer of ownership and saw the same result. Are there any additional steps to these that needed to be performed?

    3. The .cmd linker files that needs to be updated. I am not quite clear as to what updates need to be made for this files. I have taken the same file that is being given in in ti folder under : D:\ti\ccs1240\ccs\ccs_base\c2000\include. Could you please suggest modifications about what changes to do in the same to enable the entry point to code of CPU2 in flash after reset? NOTE: I have included the CodeSTartBranch.asm file.

    And lastly, are all these 3 steps required together to perform dual core flash programming without debugger and successful runs on reset or are these the 3 different solutions to the same problem?

    I am a beginner using this DSP, so exploring it. It will be helpful if you kindly answer the questions

    Thanks, 

    Prarambhik

  • 0 in reply to MatthewPate
    Prodigy 55 points

    Hi Matthew,

    Just to follow up, I mistakenly clicked the "this resolved my issue" while replying to you. Can we please continue the discussion over this thread or do I need to create a seperate one ?

    Thanks,

    Prarambhik

  • 0 in reply to Prarambhik Sur
    TI__Guru* 81500 points

    Prarambhik,

    Yes we can continue using this thread, no need to refile.  Let me look over your latest reply and get back to you here.

    Matt

  • 0 in reply to MatthewPate
    Prodigy 55 points

    Hello Matthew,

    Thanks for the confirmation. Waiting for your feedback on the queries.

    Prarambhik

  • +1 in reply to Prarambhik Sur
    TI__Guru* 81500 points

    Prarambhik,

    For Q1, this is just set up to differentiate between booting from flash and ram as CPU1 directs CPU2 what to do.  If you want CPU2 to boot differently then you can change the argument in this function.  If everything is already loaded to flash on both cores you can leave this as is for flash boot

    The boot control pins are programmed into OTP(One Time Programmable) memory, this is why you are not seeing these change correctly when you try to write them in your code.  If you open the flash tools in CCS, there is a place to program these locations directly.

    Below are the addresses, but I would recommend just using the flash tool for this.

    I would start with a .cmd file that is already pre-made for CPU2_flash execution.  You should see this file in that same path as above; 2837xD_FLASH_lnk_cpu2.cmd  It will have the code entry points setup correctly.

    Best,
    Matthew

  • 0 in reply to MatthewPate
    Prodigy 55 points

    Hi Matthew,

    Apologize for the delayed reply. I tried using the linker cmd files that were already available and was unable to boot CPU2 after reset. I still believe the entry point of the code in CPU2 is not getting identified properly and its in wait state after BOOT_ROM code execution (maybe).

    Henceforth, I tried with IPC handshaking between the two cores and it worked. Now I am able to get both CPU1 and CPU2 boot up after reset of power to the DSP.

    Thanks for resolving the queries.

    Regards,

    Prarambhik