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TMS320F28388D: SysCtl_setCLBClk function only allows 1 CLB to be configured

Jennifer Stander
Intellectual 510 points

Part Number: TMS320F28388D

Hi,

Ideally we wanted to run the CLB off of the 200 MHz system clock, however the TRM indicates that it can only run at 150 MHz. 
Can you confirm, we can not run the CLB off of the 200 MHz system clock in the F28388 device?

If this is the case, then we tried to run the CLBs in ASYNC mode dividing our 500 MHz AUXPLL down to 100 MHz. 

We are using the SysCtl_setCLBClk function and we want to configure CLB 3 and CLB4 to run ASYNC. 

So we issue the function twice, first for CLB3 and second for CLB4.

However, the call for CLB4 overwrites the setting for CLB3 setting it back to SYNC mode. 

The comments for the SysCtl_setCLBClk indicate that only one enumerated value can be entered in the inst argument. 

Please advise, if I want to configure multiple CLBs to use SYSCTL_CLBCLK_ASYNC what do you recommend?

A previous ticket indicated the function might need to be updated but we checked the sysctl.h file in the latest version and it is the same. 

Should we write our own function to configure the CLB clock to ASYNC on multiple CLB or is there a way to do this using TI provided function calls?

This seems like a very common thing to do to have it broken and I want to make sure I wasn't misunderstanding something. 

Thank you, 

Jennifer

Jennifer

  • 0
    TI__Mastermind 22631 points

    Hi Jennifer,

    That is correct, the maximum rated frequency of the CLB clock is 150 MHz if you are dividing the 200 MHz SYSCLK by 2 and enabling PIPELINE mode. Any faster and you are overclocking the IP in which case we cannot guarantee correct performance of the CLB. 

    Can you provide the post which you are mentioning about the previous ticket? Let me look into our issue tracking system to see on the status of that.

    Regards,

    Peter

  • 0 in reply to Jennifer Stander
    TI__Mastermind 22631 points

    Hi Jennifer,

    I looked through our issue tracker and wasn't able to locate this - please allow me to reach out to the engineer in the previous post to see the status of that bug fix. I will try to see if I can directly provide you the required register calls to accurately set the CLB clock, while we are in the process of resolving this bug in the official DriverLib 

    Regards,

    Peter

  • 0 in reply to Peter Luong
    Intellectual 510 points

    You indicate that it is valid to use a 200 MHz SYSCLK with a PERCLKDIVSEL.EPWMCLKDIV of 2 and enabling PIPELINE mode. Please confirm this will result in a TILE Clock of 100 MHz but still run the CLB Register Clock at 200 MHz. Running the register clock at 200 MHz is OK? We still want to use ASYNC clock in the end but are looking for work arounds in the short term. 

  • 0 in reply to Jennifer Stander
    TI__Mastermind 22631 points

    Hi Jennifer,

    Yes the information you mentioned is correct. If you have the 200 MHz clock and then divide it down so that the CLB tile clock is 100 MHz, you can achieve 150 MHz CLB tile clock operation by enabling pipeline mode. This is also reflected in the datasheet. Do note that the minimum clock values will be removed in the next revision of the datasheet as you can technically run them lower if you have a larger clock divider or decrease your SYSCLK

    Regards,

    Peter

  • 0 in reply to Peter Luong
    Intellectual 510 points

    Is activity on this question still in process? We rewrote the SysCtl_setCLBClk function to allow configuring multiple CLB's at once and it seems to be working. However, it is unsettling that the original function did not work properly when calling it twice consecutively. Is there more information pending?

  • +1 in reply to Jennifer Stander
    TI__Mastermind 22631 points

    Hi Jennifer,

    Are you using the latest version of our driverlib? I spoke with my colleague and he confirmed that this should be resolved. There are currently 3 functions now in the SYSCTL driverlib for manipulating the CLB clock. See below:

    //*****************************************************************************
//
//! Sets up CLB CLK dividers & configurations for a particuler CLB.
//!
//! \param divider is the value that configures the clock divider.
//! \param tdivider is the value that configures the tile clock divider.
//! \param inst is the CLB instance that needs clock settings.
//! \param config is the mode for the clock
//!
//! This function sets up the CLB CLK configurations based on the instance
//! that is selected. There are 2 dividers that scales the "source" to CLB
//! CLK. The first one is the divider & the other the tile divider.
//!
//! The \e divider parameter can have one enumerated value from
//! SysCtl_CLBClkDivider
//! The \e tdivider parameter can have one enumerated value from
//! SysCtl_CLBTClkDivider
//! The \e inst parameter can have one enumerated value from
//! SysCtl_CLBInst
//! The \e config parameter can have one enumerated value from
//! SysCtl_CLBClkm
//!
//! \note See also \e SysCtl_setCLBClkDivider() and \e SysCtl_CLBClkConfig()
//!
//! \return None.
//
//*****************************************************************************
static inline void
SysCtl_setCLBClk (SysCtl_CLBClkDivider divider, SysCtl_CLBTClkDivider tdivider,
                  SysCtl_CLBInst inst, SysCtl_CLBClkm config)
{
    EALLOW;
    //
    //clear the CLB clk configurations
    //
    HWREG(CLKCFG_BASE + SYSCTL_O_CLBCLKCTL) =
                        (HWREG(CLKCFG_BASE + SYSCTL_O_CLBCLKCTL) &
                         ~(SYSCTL_CLBCLKCTL_CLBCLKDIV_M |
                           SYSCTL_CLBCLKCTL_TILECLKDIV |
                           (0x1UL << (uint16_t)inst)));

    //
    //set the clock configurations for the particular CLB
    //
   HWREG(CLKCFG_BASE + SYSCTL_O_CLBCLKCTL) |=
                ((uint32_t)divider << SYSCTL_CLBCLKCTL_CLBCLKDIV_S) |
                ((uint32_t)tdivider << SYSCTL_CLBCLKCTL_TILECLKDIV_S) |
                ((uint32_t)config  << (uint16_t)inst);
    EDIS;
}

//*****************************************************************************
//
//! Sets up CLB CLK dividers
//!
//! \param divider is the value that configures the clock divider.
//! \param tdivider is the value that configures the tile clock divider.
//!
//! This function sets up the CLB CLK dividers.
//! There are 2 dividers that scales the "source" to CLB CLK. The first one is
//! the divider & the other the tile divider.
//!
//! The \e divider parameter can have one enumerated value from
//! SysCtl_CLBClkDivider
//! The \e tdivider parameter can have one enumerated value from
//! SysCtl_CLBTClkDivider
//!
//! \return None.
//
//*****************************************************************************
static inline void
SysCtl_setCLBClkDivider(SysCtl_CLBClkDivider divider,
                        SysCtl_CLBTClkDivider tdivider)
{
    EALLOW;

    //
    // Clear the CLB clk configurations
    //
    HWREG(CLKCFG_BASE + SYSCTL_O_CLBCLKCTL) =
                        (HWREG(CLKCFG_BASE + SYSCTL_O_CLBCLKCTL) &
                         ~(SYSCTL_CLBCLKCTL_CLBCLKDIV_M |
                           SYSCTL_CLBCLKCTL_TILECLKDIV));

    //
    // Set the clock dividers
    //
    HWREG(CLKCFG_BASE + SYSCTL_O_CLBCLKCTL) |=
                ((uint32_t)divider << SYSCTL_CLBCLKCTL_CLBCLKDIV_S) |
                ((uint32_t)tdivider << SYSCTL_CLBCLKCTL_TILECLKDIV_S);
    EDIS;
}

//*****************************************************************************
//
//! Sets up CLB CLK configurations for a particuler CLB.
//!
//! \param inst is the CLB instance that needs clock settings.
//! \param config is the mode for the clock
//!
//! This function sets up the CLB CLK configurations based on the instance
//! that is selected.
//!
//! The \e inst parameter can have one enumerated value from
//! SysCtl_CLBInst
//! The \e config parameter can have one enumerated value from
//! SysCtl_CLBClkm
//!
//! \return None.
//
//*****************************************************************************
static inline void
SysCtl_CLBClkConfig(SysCtl_CLBInst inst, SysCtl_CLBClkm config)
{
    EALLOW;

    //
    // Clear the CLB clk configurations
    //
    HWREG(CLKCFG_BASE + SYSCTL_O_CLBCLKCTL) =
                        (HWREG(CLKCFG_BASE + SYSCTL_O_CLBCLKCTL) &
                         ~(0x1UL << (uint16_t)inst));

    //
    // Set the clock configurations for the particular CLB
    //
    HWREG(CLKCFG_BASE + SYSCTL_O_CLBCLKCTL) |=
                        ((uint32_t)config  << (uint16_t)inst);
    EDIS;
}

    Regards

    Peter

  • 0 in reply to Peter Luong
    Intellectual 510 points

    Thank you for pointing out the additional functions. These look like what we were looking for.