TMS320F28379D: Limiting Core Access

Ed Sanders

Greetings,

Is there a way to restrict a developer, who is using CCS to debug code, so that only one core can be accessed and the other not seen?

Thank you,

over 2 years ago

0 Omer Amir over 2 years ago

TI__Mastermind 30185 points

Hello Ed,

How are you trying to limit the access, and for what purpose? Are you just trying to secure the memory or are you trying to prevent another core from being run? Is this purely for debugging or is this for a device that will be released and should not have any access to it?

Best regards,

Omer Amir

0 Ed Sanders over 2 years ago in reply to Omer Amir

Genius 4175 points

Hi Omer,

We are hiring a contractor who will be using CCS to write code which runs on Core 2. We want to hide our IP on Core 1, and as much as possible on Core 2. If there is a way to set up CCS to only allow access to the core on which the development will be occurring, that would help a lot.

Thanks,

+1 Ki over 2 years ago in reply to Ed Sanders

TI__Guru**** 482361 points

Hi Ed,

You can hide a CPU from the debug view so it is not visible (see the "Debug Configurations" section of: https://dev.ti.com/tirex/explore/node?node=A__AF77MYXC5GXV9l1NS.Clig__ccs_devtools__FUz-xrs__LATEST)

You can also create a target configuration file where the first CPU is set as BYPASS, hence the debugger will not have debug access to it.

However, in both cases, the action can easily be undone. So this is likely not helpful.

0 Ed Sanders over 2 years ago in reply to Ki

Genius 4175 points

Thank you Ki. This is better than nothing, and I think will have the added benefit of reducing distractions in the debug session.

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TMS320F28379D: Limiting Core Access