This is the follow up question of below thread
So as stated in Last comment of above thread
1. we tried enabling ecc and programing but it is unsuccessful as chunks of data is been left not written booting is unsuccessful, all sectors are align by 8, please find linker file below
MEMORY
{
/* Flash sectors */
CMBANK0_RESETISR : origin = 0x00200000, length = 0x00000064 /* Boot to Flash Entry Point */
CMBANK0_SECTOR0 : origin = 0x00200064, length = 0x00003F93
CMBANK0_SECTOR1 : origin = 0x00204000, length = 0x00004000
CMBANK0_SECTOR2 : origin = 0x00208000, length = 0x00004000
CMBANK0_SECTOR3 : origin = 0x0020C000, length = 0x00004000
CMBANK0_SECTOR4 : origin = 0x00210000, length = 0x00010000
CMBANK0_SECTOR5 : origin = 0x00220000, length = 0x00010000
CMBANK0_SECTOR6 : origin = 0x00230000, length = 0x00010000
CMBANK0_SECTOR7 : origin = 0x00240000, length = 0x00010000
CMBANK0_SECTOR8 : origin = 0x00250000, length = 0x00010000
CMBANK0_SECTOR9 : origin = 0x00260000, length = 0x00010000
CMBANK0_SECTOR10 : origin = 0x00270000, length = 0x00004000
CMBANK0_SECTOR11 : origin = 0x00274000, length = 0x00004000
CMBANK0_SECTOR12 : origin = 0x00278000, length = 0x00004000
CMBANK0_SECTOR13 : origin = 0x0027C000, length = 0x00004000
C1RAM : origin = 0x1FFFC000, length = 0x00001FFF
C0RAM : origin = 0x1FFFE000, length = 0x00001FFF
BOOT_RSVD : origin = 0x20000000, length = 0x00000800 /* Part of S0, BOOT rom will use this for stack */
SRAM : origin = 0x20000800, length = 0x0000F7FF
E0RAM : origin = 0x20010000, length = 0x00003FFF
CPU1TOCMMSGRAM0 : origin = 0x20080000, length = 0x00000800
CPU1TOCMMSGRAM1 : origin = 0x20080800, length = 0x00000800
CMTOCPU1MSGRAM0 : origin = 0x20082000, length = 0x00000800
CMTOCPU1MSGRAM1 : origin = 0x20082800, length = 0x00000800
CPU2TOCMMSGRAM0 : origin = 0x20084000, length = 0x00000800
CPU2TOCMMSGRAM1 : origin = 0x20084800, length = 0x00000800
CMTOCPU2MSGRAM0 : origin = 0x20086000, length = 0x00000800
CMTOCPU2MSGRAM1 : origin = 0x20086800, length = 0x00000800
}
SECTIONS
{
.resetisr : > CMBANK0_RESETISR,FILL=0
.vftable : > CMBANK0_SECTOR3,ALIGN(16) /* Application placed vector table in Flash, this shall not be collided with any other flash sectors*/
.vtable : > E0RAM /* Application placed vector table in RAM*/
.text : >> CMBANK0_SECTOR2,ALIGN(16)
.cinit : > CMBANK0_SECTOR1,ALIGN(16)
.pinit : >> CMBANK0_SECTOR0 | CMBANK0_SECTOR1,ALIGN(16)
.switch : >> CMBANK0_SECTOR0 | CMBANK0_SECTOR1,ALIGN(16)
.text : > CMBANK0_SECTOR3, PAGE= 0, ALIGN(16) /* Here ALIGN(8) makes sure that .text section starts on a 128-bit aligned memory address*/
//.text : > CMBANK0_SECTOR3, PAGE= 0, ALIGN(8)
.sysmem : > E0RAM
.binit : > CMBANK0_SECTOR1
.stack : > C0RAM
.ebss : > C0RAM
.econst : >> CMBANK0_SECTOR0 | CMBANK0_SECTOR1 ,ALIGN(16)
.esysmem : > C0RAM
.data : > E0RAM
.bss : > E0RAM
.const : {} LOAD = CMBANK0_SECTOR0 | CMBANK0_SECTOR1 |CMBANK0_SECTOR2 ,ALIGN(16)
RUN = E0RAM,
LOAD_START(constLoadStart),
LOAD_SIZE(constLoadSize),
LOAD_END(constLoadEnd),
RUN_START(constRunStart),
RUN_SIZE(constRunSize),
RUN_END(constRunEnd)
MSGRAM_CM_TO_CPU1 : > CMTOCPU1MSGRAM0, type=NOINIT
MSGRAM_CM_TO_CPU2 : > CMTOCPU2MSGRAM0, type=NOINIT
MSGRAM_CPU1_TO_CM : > CPU1TOCMMSGRAM0, type=NOINIT
MSGRAM_CPU2_TO_CM : > CPU2TOCMMSGRAM0, type=NOINIT
.TI.ramfunc : {} LOAD = CMBANK0_SECTOR0 | CMBANK0_SECTOR1 | CMBANK0_SECTOR2 ,
RUN = E0RAM,
LOAD_START(RamfuncsLoadStart),
LOAD_SIZE(RamfuncsLoadSize),
LOAD_END(RamfuncsLoadEnd),
RUN_START(RamfuncsRunStart),
RUN_SIZE(RamfuncsRunSize),
RUN_END(RamfuncsRunEnd),
ALIGN(8)
}
/*
//===========================================================================
// End of file.
//===========================================================================
*/2. Can you please review the code and point out where i need to make changes to program flash successfully in enable ecc method
data will come from CPU1 IPC in 1024 chunks goes to copy data function ,there on 8 bytes of data will get passed and written on to flash through Flash_data_program_8 function
//Main //
int main(void)
{
Fapi_FlashStatusWordType oFlashStatusWord;
// ///////////////////////////////////////
// Initializing the CM. Loading the required functions to SRAM.
//
CM_init();
isWD_Reset();
//
// Enable processor interrupts.
//
Interrupt_enableInProcessor();
//CM- CPU1
IPC_clearFlagLtoR(IPC_CM_L_CPU1_R, IPC_FLAG_ALL);
IPC_registerInterrupt(IPC_CM_L_CPU1_R, IPC_INT0, IPC_CPU1_CM_ISR0);
//falsh module initialization//
Flash_initModule(FLASH0CTRL_BASE, FLASH0ECC_BASE, 2);
initFlashSectors();
Flash_enableECC(FLASH0ECC_BASE);
// Flash_disableECC(FLASH0ECC_BASE);
Flash_claimPumpSemaphore(FLASH_CM_WRAPPER);
while(1)
{
Fapi_doBlankCheck((uint32_t *)0x0027C000, 1, &oFlashStatusWord);
if((oFlashStatusWord.au32StatusWord[1] & 0x0000FFFF) == BOOT_MODE_CD_WORD)
{
if( (!gis_WD_Reset) )
{
IPC_sync(IPC_CM_L_CPU1_R, IPC_FLAG28);
IPC_sync(IPC_CM_L_CPU2_R, IPC_FLAG29);
}
Flash_releasePumpSemaphore();
entryAddress = 0x210001;
( (void (*)(void))entryAddress)();
}
else
{
;
}
}
}
//Flash Sector initialization//
void initFlashSectors(void){
Fapi_StatusType oReturnCheck;
//
// Initialize the Flash API by providing the Flash register base address
// and operating frequency(in MHz).
// This function is required to initialize the Flash API based on CM
// operating frequency before any other Flash API operation can be performed.
// This function must also be called whenever System frequency or RWAIT is
// changed.
//
oReturnCheck = Fapi_initializeAPI(F021_CPU0_BASE_ADDRESS,
CM_CLK_FREQ/1000000U);
if(oReturnCheck != Fapi_Status_Success)
{
//
// Check Flash API documentation for possible errors
//
// exampleError(oReturnCheck);
}
//
// Initialize the Flash banks and FMC for erase and program operations.
// Fapi_setActiveFlashBank() function sets the Flash banks and FMC for
// further Flash operations to be performed on the banks.
//
oReturnCheck = Fapi_setActiveFlashBank(Fapi_FlashBank0);
if(oReturnCheck != Fapi_Status_Success)
{
//
// Check Flash API documentation for possible errors
//
// exampleError(oReturnCheck);
}
}
bool Flash_data_program_8(uint32 Flash_sector, uint8 *Buffer, uint8 words)
{
// uint16 i = 0;
uint32 u32Index = 0;
// uint16 i = 0;
uint32 *Buffer32 = (uint32 *) Buffer;
Fapi_StatusType oReturnCheck;
volatile Fapi_FlashStatusType oFlashStatus;
Fapi_FlashStatusWordType oFlashStatusWord;
if((Flash_sector >= 0x00210000) && (Flash_sector <= 0x00278000) )
{
oReturnCheck = Fapi_initializeAPI(F021_CPU0_BASE_ADDRESS,
200);
if(oReturnCheck != Fapi_Status_Success)
{
//
// Check Flash API documentation for possible errors
//
// return false;
// Example_Error(oReturnCheck);
}
//
// Initialize the Flash banks and FMC for erase and program operations.
// Fapi_setActiveFlashBank() function sets the Flash banks and FMC for
// further Flash operations to be performed on the banks.
//
oReturnCheck = Fapi_setActiveFlashBank(Fapi_FlashBank0);
if(oReturnCheck != Fapi_Status_Success)
{
// return false;
//
// Check Flash API documentation for possible errors
//
// Example_Error(oReturnCheck);
}
oReturnCheck = Fapi_issueProgrammingCommand((uint32 *)Flash_sector,Buffer,
words, 0, 0, Fapi_DataOnly);
//
// Wait until the Flash program operation is over
//
while(Fapi_checkFsmForReady() == Fapi_Status_FsmBusy);
if(oReturnCheck != Fapi_Status_Success)
{
// return false;
//
// Check Flash API documentation for possible errors
//
// Example_Error(oReturnCheck);
}
//
// Read FMSTAT register contents to know the status of FSM after
// program command to see if there are any program operation related
// errors
//
oFlashStatus = Fapi_getFsmStatus();
if(oFlashStatus != 0)
{
// return false;
//
// Check FMSTAT and debug accordingly
//
// FMSTAT_Fail();
}
//
// Verify the values programmed. The Program step itself does a verify
// as it goes. This verify is a 2nd verification that can be done.
//
// oReturnCheck = Fapi_doVerify((uint32 *) Flash_sector, words / 4,
// Buffer, &oFlashStatusWord);
//
// if (oReturnCheck != Fapi_Status_Success)
// {
// return FALSE;
// // Example_Error(oReturnCheck);
// }
oReturnCheck = Fapi_doVerifyByByte((uint32_t *)Flash_sector, words, Buffer, &oFlashStatusWord);
if (oReturnCheck != Fapi_Status_Success)
{
write_status[2]=1;
write_status[5] =iteration_cnt;
return false;
}
return true;
}
write_status[4] = iteration_cnt;
return false;
}
/**
* @brief: this function it will handle the given hex data as per boot structure of TI controller
* it will validate key value and then write hex data as given block size and block address.
* @author <19 FEB 2021 ; Basweshwar >
* @return after successful completion return TRUE otherwise FALSE.
*/
#ifdef __cplusplus
#pragma CODE_SECTION(".TI.ramfunc");
#else
#pragma CODE_SECTION(copy_data, ".TI.ramfunc");
#endif
bool copy_data(uint8_t * aBuffer)
{
/* this function it will handle the given hex data as per boot structure of TI controller
* it will validate key value and then write hex data as given block size and block address by
* calling Flash_data_program_8 function*/
}
Thanks and Regards
Pranay
