TMS320F28035: Default pull-up disabled pins getting high for short time.

Hello Madhu,

Can you confirm is this only happening upon power-up or every time the device is reset? How long is this high GPIO signal lasting for?

Best regards,

Omer Amir

Hello Mr.Amir,

As I'm facing another issue while flashing or debugging mentioned in TMS320F28035: Flashing issue in TMS320F28035. Device locked, I've not tried another unit to run in debug mode.

So, the issue I've mentioned is during power up of Unit. Device won't be reset until power is OFF.

The below picture is of GPIO7 pin when unit is powered up. It can be seen that it is high for 32.56msec.

Best regards,

Madhu

Hello Madhu,

Based on a discussion I had with a design expert, the boot code may make all IO pull-ups enabled by default, so even though it is disabled by hardware, the boot software will enable it. I've reached out to a boot ROM expert to see if this is the case and whether anything can be done about this.

Best regards,

Omer Amir

Hello Mr.Amir,

We would also like to understand on why this is happening in few units even though all the hardware and Software remains same.

Thanks & regards,

Madhu P 

Hello Madhu,

Based on what the boot ROM expert told me, the ROM will only pull up unbonded GPIOs (pins not available for the specific package). To narrow down this issue further, have you already monitored that nothing else besides power is connected to the board when you turn it on/startup your code? Have you monitored the power and ground rails of the device (i.e. VDD, VDDIO, VSS)?

Best regards,

Omer Amir

Madhu,

          Are you using the on-chip VREG or are you supplying 1.8v externally? If it is the latter, are you following the requirement in page 12 of www.ti.com/lit/SPRS584?

"There is no power-sequencing requirement when using an external 1.8-V supply.

However, if the 3.3-V transistors in the level-shifting output buffers of the I/O pins are powered before

the 1.8-V transistors, it is possible for the output buffers to turn on, causing a glitch to occur on the pin

during power up. To avoid this behavior, power the VDD pins before or with the VDDIO pins, ensuring

that the VDD pins have reached 0.7 V before the VDDIO pins reach 0.7 V."

Hello Madhu,

In addition to a scope of your supplies, can you tell me is there anything besides power and a debug connection connected to the device? Is this glitch issue happening on all GPIO that have the pull-up disabled by default, or only certain ones?

Best regards,

Omer Amir

Hi Madhu, from the other thread we learned you are using internal VREG to power the 1.8V supply.  In that case we can dismiss the power sequencing concern for now.  That said it does appear the 12V supply is not fully powered by the time the F28035 is powered and presumably reset is de-asserted.  I'm not saying that is related to GPIO7 but could mean some external devices the F28035 is interacting with are not ready.  That is just an observation.  Of course you may have an external supervisor holding F28035 in reset until the rest of the system is verified ready.  i cannot tell from the power supply image in the other thread.

To debug the GPIO7 issue further, we would like to understand a few things about the behavior:

1) For a device which shows the unexpected toggle of GPIO7, does it occur on every power up?

2) How much passes from XRSn going high and the GPIO7 toggle?

3) Does it occur only on power-on reset or also on a warm reset (manual assertion and release of XRSn).  Now that the flash issue is resolved, I'm hoping you can try this on a board?

4) Are you using INTOSC or XTAL for clocking F28035?

regards,

Joe

Hello Mr.Joe,

Sorry for the delayed response. As we have caught up with the other issues I couldn't replied to your queries. Please find the answers below

Regarding controller supply, as there is a LDO for 3.3V, once the 12V supply builds around 7V it will give 3.3V output.

1) For a device which shows the unexpected toggle of GPIO7, does it occur on every power up?

     It happens on every power up.

2) How much passes from XRSn going high and the GPIO7 toggle?

     This we will check and confirm with you

3) Does it occur only on power-on reset or also on a warm reset (manual assertion and release of XRSn).  Now that the flash issue is resolved, I'm hoping you can try this on a board?

    It is happening on every Power ON reset. With the JTAG after flashing and run it in debug mode relay turning on is not happening. So, the issue observed is when there is a power reset

4) Are you using INTOSC or XTAL for clocking F28035?

    We are using External Oscillator of 20MHz

Madhu,

            For a device that exhibits the problem consistently, please attach a scope shot that clearly shows the following signals: 3.3v, -XRS, GPIO6 & GPIO7. The scope-shot should clearly show the ramp for 3.3v and -XRS signals and the delay between -XRS inactive and the toggling of the GPIO signals.