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TMS320F28377D: Memory allocation

P C
Prodigy 135 points
Part Number: TMS320F28377D

Hi,

I want to run a program in CPU1 (not in CLA1) of the 28377D and I want the maximum amount of RAM to store the program and the data structures. Consequently, I have the following questions:

1) In the 28377D, the LSx, Dx and GSx memories have contiguous addresses. But is it possible to allocate a data section or a software section in [ LS5 + D0 + D1 + GS0]  even if these memories have not the same functionalities ?

2) Is it possible to run in CPU1 a software allocated in LSx memory whithout any restriction of the software instruction set (as it is the case for the CLA1).

Thanks for your help.

Best regards.

  • 0
    TI__Mastermind 30185 points

    Hello Philippe,

    P C said:
    1) In the 28377D, the LSx, Dx and GSx memories have contiguous addresses. But is it possible to allocate a data section or a software section in [ LS5 + D0 + D1 + GS0]  even if these memories have not the same functionalities ?

    Yes, this is allowed (be cautious that this is only for data, doing this for functions can cause issues when jumping/branching).

    P C said:
    2) Is it possible to run in CPU1 a software allocated in LSx memory whithout any restriction of the software instruction set (as it is the case for the CLA1).

    If you're asking whether you can run a program from RAM, yes this is possible; you can run a program from RAM or Flash. This does not limit the instruction set allowed (although running from Flash does introduce wait states, inherently making the program run slower).

    Best regards,

    Omer Amir

  • 0 in reply to Omer Amir
    Prodigy 135 points

    Thank you for the answer.

    1) You indicate "... doing this for functions can cause issues when jumping/branching" => could you add precisions please. What kind of issue can occur ?
    Is it impossible to perform a branch/jump from the LS5 memory to the GS0 memory  (or from GS0 to LS5) ?

    2) I would like to know if the LSx memory has a particular constraint for the instruction set:

    - when the CLA1 is running a program in LSx, the instruction set is limited
    - but when the CPU1 is running a program in LSx, could you confirm that the instruction set is not limited as for CLA1.

    Thanks for your help.

    Best regards.

  • 0 in reply to P C
    TI__Mastermind 30185 points

    Hello Philippe,

    P C said:
    1) You indicate "... doing this for functions can cause issues when jumping/branching" => could you add precisions please. What kind of issue can occur ?

    I don't remember the exact error code, but essentially while debugging you will see the program enter and illegal operations ISR and/or be stuck on an ITRAP instruction in the Disassembly view.

    P C said:
    Is it impossible to perform a branch/jump from the LS5 memory to the GS0 memory  (or from GS0 to LS5) ?

    Yes, as long as it's not 1 function split across the two memory units.

    P C said:
    2) I would like to know if the LSx memory has a particular constraint for the instruction set:

    For C28x there is no restrictions on this as far as I have seen (I don't know why there would be either).

    Best regards,

    Omer Amir

  • 0 in reply to Omer Amir
    Prodigy 135 points

    Would you like to say:

    Yes IT IS POSSIBLE to perform a branch/jump, as long as it's not 1 function split across the two memory units ?

    Thanks for your help

  • 0 in reply to P C
    TI__Mastermind 30185 points

    Hello Philippe,

    Yes, that is correct; this is the reason that a program can be partially in RAM and Flash (as long timing is not too important for the program at least).

    Best regards,

    Omer Amir