TMS320F280039C: clocking frequency

Hello, Thanks for reaching out!

For configuring the system clock to 120 Mhz configure PLL as per application needs you can use the dividers namely : ODIV, IMULT and REFDIV refer to equation and diagram Figure 6-10. System PLL in TMS320F28003x Real-Time Microcontrollers datasheet. 

Note: Configuration should be such the internal clock frequencies follow the guidelines in 6.12.3.2.1.8 Internal Clock Frequencies in TMS320F28003x Real-Time Microcontrollers datasheet. 

To view the system PLL clock on scope you can use XCLKOUT and output the selected clock frequency on available GPIO but the max limit is 50Mhz so you wont be able to monitor any frequencies higher than that. To use XCLKOUT, first select the clock source via the CLKSRCCTL3 register. Next, select the desired output divider via the XCLKOUTDIVSEL register. Finally, connect GPIO16 or GPIO18 to mux channel 11 using the GPIO configuration registers.

Thanks,
Prarthan.

Thanks for the reply

Is there any way to see the Maximum clock frequency 120MHz, Because oscilloscope supports the maximum frequency of 200Mhz.

Hello Prem,

To view the system PLL clock on scope you can use XCLKOUT and output the selected clock on available GPIO's as mentioned above but when you have frequency greater than 50Mhz (you could still be able to see the frequency) the pulse would be truncated because of GPIO limitation.

Greetings 

Is there any other way to see the maximum clock frequency (120MHz) produced by controller, except by checking the register values. 

Prem,

The method I suggested above is to route the clock on gpio and observe the clock output from it, its not register based.

To route clock out on GPIO you would need to configure appropriately. Refer to below steps :
"The external clock output (XCLKOUT) feature supports this by connecting a clock to an external pin, which can be GPIO16 or GPIO18. The available clock sources are PLLSYSCLK, PLLRAWCLK, SYSCLK, INTOSC1, INTOSC2, and XTAL. To use XCLKOUT, first select the clock source via the CLKSRCCTL3 register. Next, select the desired output divider via the XCLKOUTDIVSEL register. Finally, connect GPIO16 or GPIO18 to mux channel 11 using the GPIO configuration registers."