Part Number: TMS320F280025C
Hi Champ,
I am asking for my customer.
The are trying to implement the DCL example (NLPID) with the customized FLASH .cmd configuration. Customer doesn't modify the main code in example, only pre-define _FLASH.
The project is built successfully and programmed into device properly w/o error. However, once it programmed, it couldn't run the code with the resume button.
Clicking the TI XDS110 USB Debug Probe in debug window, then suspend the code. It would jump out No source available for "SysCtl_delay() at ~\F280025_NLPID\CPU1_RAM\F280025_NLPID.out:{3} 0xc057{4}".
Below is the FLASH .cmd. configuration from customer.
MEMORY
{
PAGE 0 :
BEGIN : origin = 0x000000, length = 0x000002
RAMM0 : origin = 0x0000F5, length = 0x00030B
RAMLS456 : origin = 0x00A000, length = 0x001800
RESET : origin = 0x3FFFC0, length = 0x000002
/* BANK 0 */
FLASH_BANK0_SEC0 : origin = 0x080000, length = 0x001000
FLASH_BANK0_SEC1 : origin = 0x081000, length = 0x001000
// FLASH_BANK0_SEC2 : origin = 0x082000, length = 0x001000
// FLASH_BANK0_SEC3 : origin = 0x083000, length = 0x001000
// FLASH_BANK0_SEC4 : origin = 0x084000, length = 0x001000
// FLASH_BANK0_SEC5 : origin = 0x085000, length = 0x001000
FLASH_BANK0_SEC2_5 : origin = 0x082000, length = 0x004000
FLASH_BANK0_SEC6 : origin = 0x086000, length = 0x001000
FLASH_BANK0_SEC7 : origin = 0x087000, length = 0x001000
FLASH_BANK0_SEC8 : origin = 0x088000, length = 0x001000
FLASH_BANK0_SEC9 : origin = 0x089000, length = 0x001000
FLASH_BANK0_SEC10 : origin = 0x08A000, length = 0x001000
FLASH_BANK0_SEC11 : origin = 0x08B000, length = 0x001000
FLASH_BANK0_SEC12 : origin = 0x08C000, length = 0x001000
FLASH_BANK0_SEC13 : origin = 0x08D000, length = 0x001000
FLASH_BANK0_SEC14 : origin = 0x08E000, length = 0x001000
FLASH_BANK0_SEC15 : origin = 0x08F000, length = 0x001000
/* BANK 1 */
// FLASH_BANK1_SEC0 : origin = 0x090000, length = 0x001000
// FLASH_BANK1_SEC1 : origin = 0x091000, length = 0x001000
// FLASH_BANK1_SEC2 : origin = 0x092000, length = 0x001000
FLASH_BANK1_SEC3 : origin = 0x093000, length = 0x001000
FLASH_BANK1_SEC4 : origin = 0x094000, length = 0x001000
FLASH_BANK1_SEC5 : origin = 0x095000, length = 0x001000
FLASH_BANK1_SEC6 : origin = 0x096000, length = 0x001000
FLASH_BANK1_SEC7 : origin = 0x097000, length = 0x001000
FLASH_BANK1_SEC8 : origin = 0x098000, length = 0x001000
FLASH_BANK1_SEC9 : origin = 0x099000, length = 0x001000
FLASH_BANK1_SEC10 : origin = 0x09A000, length = 0x001000
FLASH_BANK1_SEC11 : origin = 0x09B000, length = 0x001000
FLASH_BANK1_SEC12 : origin = 0x09C000, length = 0x001000
FLASH_BANK1_SEC13 : origin = 0x09D000, length = 0x001000
FLASH_BANK1_SEC14 : origin = 0x09E000, length = 0x001000
FLASH_BANK1_SEC15 : origin = 0x09F000, length = 0x001000
PAGE 1 :
BOOT_RSVD : origin = 0x000002, length = 0x0000F3
RAMM1 : origin = 0x000400, length = 0x000400
RAMLS7a : origin = 0x00B800, length = 0x000400
RAMLS7b : origin = 0x00BC00, length = 0x000400
RAMGS0a : origin = 0x00C000, length = 0x000400
RAMGS0b : origin = 0x00C400, length = 0x000400
FLASH_BANK1_SEC0_1_2 : origin = 0x090000, length = 0x003000
}
SECTIONS
{
codestart : > BEGIN, ALIGN(8)
.text : > FLASH_BANK0_SEC2_5, ALIGN(8)
.cinit : > FLASH_BANK0_SEC1, ALIGN(8)
.switch : > FLASH_BANK0_SEC1, ALIGN(8)
.reset : > RESET, TYPE = DSECT /* not used, */
.stack : > RAMM1
.init_array : > FLASH_BANK0_SEC1, ALIGN(8)
.bss : > RAMGS0b
.bss:output : > RAMGS0b
.bss:cio : > RAMGS0b
.const : > FLASH_BANK0_SEC1, ALIGN(8)
.data : > RAMGS0b
.sysmem : > RAMGS0b
.TI.ramfunc : LOAD = FLASH_BANK0_SEC1,
RUN = RAMLS456,
LOAD_START(RamfuncsLoadStart),
LOAD_SIZE(RamfuncsLoadSize),
LOAD_END(RamfuncsLoadEnd),
RUN_START(RamfuncsRunStart),
RUN_SIZE(RamfuncsRunSize),
RUN_END(RamfuncsRunEnd),
ALIGN(8)
dclfuncs : > FLASH_BANK0_SEC1, PAGE = 0 align(4)
pDataLogSection : > FLASH_BANK1_SEC0_1_2, PAGE = 1 align(4)
qDataLogSection : > FLASH_BANK1_SEC0_1_2, PAGE = 1 align(4)
sDataLogSection : > FLASH_BANK1_SEC0_1_2, PAGE = 1 align(4)
}
/*
//===========================================================================
// End of file.
//===========================================================================
*/
Is there any problem with the .cmd file ? Any suggestion to address the issue ?
Thanks and regards,
Johnny
