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TMS320F28386D: TALK bit in SCI

Francisco Felip
Prodigy 20 points
Part Number: TMS320F28386D


Hi all

I'm debugging an application with SCI communication using the FIFO enhancements for TX and RX. I've found that, occasionally, the for loop in which the transmit buffer is written to 16 times (to fill the TX FIFO) is interrumped by a HWI, causing an idle time between bytes in the frame that the other controller involved in the transmission interprets as a faulty frame. This is caused by the peripheral trying to empty the FIFO as soon as it has anything to be sent.

I have been looking for something in the SCI register that would allow me to block transmission as I write into the FIFO, and then allow back transmission as soon as the FIFO is full, so the frame is delayed but its bytes are sent back to back, which is the desired behaviour. Something akin to what the TALK bit does in SPI.

I've tried disabling TX and FIFO enhancements but apparently the FIFO can't be written to if any of those is cleared. Any ideas on how to implement this?

Thanks

  • 0
    TI__Mastermind 19795 points

    Hi Francisco,

    Thanks for your question. Have you tried using "TXENA" bit? That seems similar to what you are looking to do.

    Regards,

    Vince

  • 0 in reply to Vince
    Prodigy 20 points

    Hi Vince,

    Thanks for the reply. Unfortunately, I've already tried this and TX FIFO seems blocked while TXENA is down. I've checked that SCIFFTX.TXFFST is 0 after writting to the buffer using this technique with TXENA. If I halt the execution while TXENA is cleared and make manual writes to SCITXBUF (using the Registers tab), TXFFST doesn't increase neither (this does happen when comms are enabled). On top of that, the comms stop working at all.

  • +1 in reply to Francisco Felip
    TI__Mastermind 19795 points

    Hi Francisco,

    I understand now, thanks for the clarification. Unfortunately the SCI module does not have the capability to do what you are wanting to do. If there was DMA access to this peripheral I would recommend that (maybe switch to using UART peripheral on CM core?). That would help you to not have to worry about idle time between bytes.

    Regards,

    Vince

  • 0 in reply to Vince
    Prodigy 20 points

    Hi Vince,

    That's a great idea, I hadn't considered using DMA. I'll be checking if using CM is viable in our project and will be definitely using DMA+UART if so. Thanks for the advice!

    Kind regards