• State Resolved
  • Locked Locked
  • Replies 3 replies
  • Subscribers 83 subscribers
  • Views 551 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS320F28377D-EP: TiMER0 and ADCINT1 ad a trigger for CLA - nesting interrupt

Laurent Z.
Intellectual 325 points

Part Number: TMS320F28377D-EP

Hello,

I have been reading about the DSP not nesting interrupt by default and I have been reading the following given link in the TRM 

http://processors.wiki.ti.com/index.php/Interrupt_Nesting_on_C28x

I am just a bit concerned about a situation within my design.

In the situation where ADCINT1 is the trigger of CLA task1, no ADC ISR, what would happen if the TIMER0 is the source of an ISR being executed?

Would the ADCINT1 still trigger the CLA TASK1 in a deterministic fashion or do we need to wait for TIMER0 ISR to end before the ADCINT1 can trigger the CLA Task?

Thank you

Laurent

  • 0
    TI__Guru* 95315 points

    Laurent,

            Could you please clarify "ADCINT1 is the trigger of CLA task1, no ADC ISR,"? 

  • 0 in reply to Hareesh Janakiraman
    Intellectual 325 points

    Using the register DmaClaSrcSelRegs.CLA1TASKSRCSELx[TASKx], I am configuring the trigger of CLA TASK1 to be the ADC End Of Conversion interrupt which is routed to ADCINT1. However, I am not routing ADCINT1 through the PIE to called an ISR.

    My concern is that the DSP could be executing code in the TIMER0 ISR while the ADCINT1 is set in the background. My understanding is that entering an ISR will disable the PIE so there is no nesting interrupt.

    However, ADCINT1 is a hardware interrupt and PIE again is not used for this interrupt, so I think it is fine but I wish to have confirmation 

    Basically I want to make sure the trigger of CLA Task1 is deterministic and will not be processed after TIMER0 ISR has ended.

  • +1 in reply to Laurent Z.
    TI__Guru* 93800 points

    The interrupt from the ADC or TIMER will go to both the PIE and the CLA at the same time. The behavior of each is independent from that point. i.e. execution of a task does not depend on what the C28x is executing at that time.