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TMS320F28384D: accessing FPGA using EMIF asynchronous 32-bit Data bus

Eyal Saban1
Intellectual 905 points

Part Number: TMS320F28384D

Dear Sir ,

1. We are developing a controller  based on TMS320F28384D  , and would like to interface to FPGA  using the EMIF that is configured as asynchronous  32-bit Data  / 12-bit Address  

2. on  a previous designs we had similar interface  between   C2000 chip  ( 28376S)  and  FPGA  but it  was   16-bit Data  / 12-bit Address , and it worked properly.

3. if we want to expand the data bus  to 32bit  (as mention in section 1  )  , do we need to use EM1DQM[1:0]  ?  assuming  all access  from the DSP  to the FPGA will be only 32-bit 

 

 

  • 0
    TI__Guru** 116041 points

    Hi,

    Eyal Saban1 said:
    3. if we want to expand the data bus  to 32bit  (as mention in section 1  )  , do we need to use EM1DQM[1:0]  ?  assuming  all access  from the DSP  to the FPGA will be only 32-bit 

    DQM are byte enable signals. Ideally one need not to use DQM signals if they are doing 32bit access but in case compiler split 32bit access into two 16bit access, it'll not work hence it may be better to use these signals. Please note that C28x is 16bit addressing so you need to use one of the byte enable from pair of 16bit. So you'll have to use one from DQM [1:0] and other one from DQM[2:3].

    Regards,

    Vivek Singh

  • 0 in reply to Vivek Singh
    Intellectual 905 points

    Hi Vivek ,

    Thank you for the quick response ,

    1. i am looking at Design and guidelines for  C2000 EMIF (SPRAC96A) , and there is remark  on 32-bit  data bus

       DMQx ..   "..Byte enable signals for 32-bit memories can also be tied low if 16-bit writes and reads are not used"   (page 7)

       my plan  is to use DMA that will be configured for 32-bit  access  , so you think  i still need it ?

    2. i can see there are  signals   DQM[1:0]  , but  what are the signals  DQM[2:3] ?  i don't see any refence (looking   at page 6  in SPRAC96A)

  • 0 in reply to Eyal Saban1
    TI__Guru** 116041 points
    Eyal Saban1 said:

    1. i am looking at Design and guidelines for  C2000 EMIF (SPRAC96A) , and there is remark  on 32-bit  data bus

       DMQx ..   "..Byte enable signals for 32-bit memories can also be tied low if 16-bit writes and reads are not used"   (page 7)

       my plan  is to use DMA that will be configured for 32-bit  access  , so you think  i still need it ?

    In this case it should be ok.

    Eyal Saban1 said:
    2. i can see there are  signals   DQM[1:0]  , but  what are the signals  DQM[2:3] ?  i don't see any refence (looking   at page 6  in SPRAC96A)

    DQM is byte enable so for 32bit interface there will be 4 byte enables. Please refer EMIF chapter in device TRM.

    Regards,

    Vivek Singh