CPU timer interrupt priorities in F28335

Alfred Zhong

Hi,

I am wondering if it is possible to set up different priorities for CPU timer interrupts.

For example, I would like to have cpu0timer > cpu1timer1 > cpu2timer

When CPU timer 0 triggers an interrupt and evoke the interrupt service routine (ISR), it can't be interrupt by timer 1 or time2's interrupts

When CPU time 1 triggers an interrupt and evoke the interrupt service routine (ISR), it can't be interrupt by time2's interrupts but can be interrupt by timer 0

When CPU time 2 triggers an interrupt and evoke the interrupt service routine (ISR), it can be interrupt by timer 0 or timer 1

It there any way to do it?

What register should I set up?

Thanks a lot!

Alfred

over 14 years ago

0 JohnS over 14 years ago

TI__Guru**** 162985 points

Alfred,

Are you using BIOS?

John

0 Alfred Zhong over 14 years ago in reply to JohnS

Intellectual 370 points

Hi John,

No, I am not using BIOS.

Thanks,

Alfred

0 JohnS over 14 years ago in reply to Alfred Zhong

TI__Guru**** 162985 points

Alfred,

Ok. I am going to move this one over to the C2000 forum. I will let the moderator know I moved it. They should be able to let you know if there is anything you can do adjusting registers to help with this.

Regards,

John

0 Frank Bormann over 14 years ago

Mastermind 7585 points

Alfred,

a temporarily modification of the IER-Register will do it.

Here is what I'd recommend to do:

interrupt void ISR_Timer0()

{

// no modification

}

interrupt void ISR_Timer1()

{

IER |= 1; // will allow timer 0 to interrupt

EINT;

// rest of ISR

}

interrupt void ISR_Timer2()

{

IER |= 0x1001; // will allow timer 0 (IER1) or timer1 (IER13) to interrupt

EINT;

// rest of ISR

}

On entry into an ISR the IER register is contect saved by hardware, wich allows us to change its content temporarily.

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CPU timer interrupt priorities in F28335