CPU timer interrupt priorities in F28335

Alfred Zhong said:

Hi, 

I am wondering if it is possible to set up different priorities for CPU timer interrupts.

For example, I would like to have cpu0timer > cpu1timer1 > cpu2timer

When CPU timer 0 triggers an interrupt and evoke the interrupt service routine (ISR), it can't be interrupt by timer 1 or time2's interrupts

When CPU time 1  triggers an interrupt and evoke the interrupt service routine (ISR), it can't be interrupt by time2's interrupts but can be interrupt by timer 0

When CPU time 2  triggers an interrupt and evoke the interrupt service routine (ISR), it can be interrupt by timer 0 or timer 1

 

It there any way to do it?

What register should I set up?

 

Thanks a lot!

Alfred

 

Please see this wiki article that describes interrupt nesting

http://processors.wiki.ti.com/index.php/Interrupt_Nesting_on_C28x

-Lori