TMS320F28035: SCI configuration for TX/RX with interrupts but without FIFO buffering

Yes, you have right that FIFO is disabled by default but how about interrupts? I see in code:

SciaRegs.SCICTL2.bit.TXINTENA =1;
SciaRegs.SCICTL2.bit.RXBKINTENA =1;

which suggest that RX/TX interrupts are enabled but if you run an Example_2803xSci_Echoback example you will see that no RX interrupt is reported - RXRDY is not set when RX recives a data.

Hi Vince. I'm using your Example_2803xSci_Echoback example which have:

SciaRegs.SCICTL1.all =0x0003;  

So TXENA and RXENA bits are set. But despite this as well as the settings:

SciaRegs.SCICTL2.bit.TXINTENA =1;
SciaRegs.SCICTL2.bit.RXBKINTENA =1;

interrupts are not reported.

Hi Vince. Sure I can, but I just thought I would run the Example_2803xSci_Echoback example with interrupts enabled and be able to test it but interrupts are not reported in this example but they should accoring to configuration:

    //
    // Note: Clocks were turned on to the SCIA peripheral in the InitSysCtrl()
    // function
    //
    
    //
    // 1 stop bit,  No loopback, No parity, 8 char bits, async mode, 
    // idle-line protocol
    //
 	SciaRegs.SCICCR.all =0x0007;   
    
    //
    // enable TX, RX, internal SCICLK, Disable RX ERR, SLEEP, TXWAKE
    //
	SciaRegs.SCICTL1.all =0x0003;  
    
	SciaRegs.SCICTL2.bit.TXINTENA =1;
	SciaRegs.SCICTL2.bit.RXBKINTENA =1;

	SciaRegs.SCIHBAUD    =0x0000;  // 9600 baud @LSPCLK = 15MHz (60 MHz SYSCLK)
    SciaRegs.SCILBAUD    =0x00C2;

	SciaRegs.SCICTL1.all =0x0023;  // Relinquish SCI from Reset

Hi WW,

Thanks for follow-up. Main reason I ask to follow the FAQ guide and then provide your results here is because if this is a hardware issue like wire connections, the scope captures mentioned in that guide will help with quickly narrowing down the issue.

So basically, scope capture of RX and TX will greatly speed up debug here, thanks!

Regards,

Vince

Hi Vince. Right now I am focusing on transmitting data so, here are my TX captures from digital analyzer.

Here is analog capture.

Here is digital capture:

Hi Vince, here are my TX and RX captures (digital and analog).

I used Example_2803xSci_Echoback example.

Hi Vince

In this situation, when I use an Example_2803xSci_Echoback example in which SCI interrupts are enabled there is no reported interrupt for RX and TX. RXRDY is not set when RX recives a data.

What I want to achieve is to modify this example to have a possibility RX and TX interrupts handling without FIFO buffering.

Hi Vince. I think we misunderstanding each other. Let me explain... I took the Example_2803xSci_Echoback example which don't have a FIFO and interrupts implemented and all I need is to have interrupts supported in this example.

Hi Vince. I know this example but I don't want a fifo support. All I want is to have SCI RX TX with interrupts but without fifo.

Hi Vince, ok, I will try this but if you say that these lines are unnecessary in case when I don't need a FIFO support then these lines are also unnecessary:

    SciaRegs.SCIFFRX.bit.RXFFOVRCLR=1;   // Clear Overflow flag
    SciaRegs.SCIFFRX.bit.RXFFINTCLR=1;   // Clear Interrupt flag

in the sciaRxFifoIsr and thse lines:

SciaRegs.SCIFFTX.bit.TXFFINTCLR=1;  // Clear SCI Interrupt flag

in the sciaTxFifoIsr. Am I right?

Vince I checked your settings. RX interrupt is reported which is OK but TX not. Interrupt empty TX buffer should be reported but it isn't.

Hi WW

WW said:

when I don't need a FIFO support then these lines are also unnecessary:

Correct, those can also be commented out.

WW said:

Interrupt empty TX buffer should be reported but it isn't.

Are there any error flags set when this happens? I wonder if this is an error interrupt triggering the ISR, and then not being cleared (which may block further interrupts from firing).

Regards,

Vince

Hi Vince I do some research. 
Right now here is my sci init function:

scia_fifo_init()
{
    //
    // 1 stop bit,  No loopback, No parity, 8 char bits, async mode,
    // idle-line protocol
    //
    SciaRegs.SCICCR.all =0x0007;

    //
    // enable TX, RX, internal SCICLK, Disable RX ERR, SLEEP, TXWAKE
    //
    SciaRegs.SCICTL1.all =0x0003;
    SciaRegs.SCICTL2.bit.TXINTENA =1;
    SciaRegs.SCICTL2.bit.RXBKINTENA =1;
    SciaRegs.SCIHBAUD = SCI_PRD >> 8;
    SciaRegs.SCILBAUD = SCI_PRD;
    //SciaRegs.SCICCR.bit.LOOPBKENA =1; // Enable loop back
    //SciaRegs.SCIFFTX.all=0xC022;
    //SciaRegs.SCIFFRX.all=0x0022;
    SciaRegs.SCIFFCT.all=0x00;

    SciaRegs.SCICTL1.all =0x0023;     // Relinquish SCI from Reset
    //SciaRegs.SCIFFTX.bit.TXFIFOXRESET=1;
    //SciaRegs.SCIFFRX.bit.RXFIFORESET=1;
}

My TX ISR:

__interrupt void
sciaTxFifoIsr(void)
{
    GpioDataRegs.GPBTOGGLE.bit.GPIO34   = 1;

    //SciaRegs.SCIFFTX.bit.TXFFINTCLR=1;  // Clear SCI Interrupt flag
    PieCtrlRegs.PIEACK.all|=0x100;      // Issue PIE ACK
}

And RX ISR:

__interrupt void
sciaRxFifoIsr(void)
{

    GpioDataRegs.GPATOGGLE.bit.GPIO31   = 1;

    znak  = SciaRegs.SCIRXBUF.all;


    PieCtrlRegs.PIEACK.all|=0x100;       // Issue PIE ack
}

And my test code which i put right before main loop:

    SciaRegs.SCITXBUF = 'a';
    DELAY_US(100000);
    SciaRegs.SCITXBUF = 'b';
    DELAY_US(100000);
    SciaRegs.SCITXBUF = 'c';

My conclusions:

RX ISR is working OK, TX ISR is reported once - right after send one character, so in this situation when I want to send a', 'b', 'c' characters the TX ISR is reported three times. Shouldn't it be reported all the time when the transmit buffer is empty?

What I want to achieve is that when TX ISR is reported - which means the TX buffor is emptied, I want to transmit some data (char array) in the TX ISR.

Hi Vince. OK, thank you for clarification. If you say that I should fill the buffer inside the TX interrupt in that case how should I trigger the TX interrupt? Which bit should I set in case when I have some array of char which I want to transmit inside the TX interrupt but I need to trigger this interrupt to start transmitting my data?

Vince if you say that TX ISR will only trigger the interrupt ONE TIME when the TX buffer is emptied - in that case I have a question about TX FIFO interrupt. When it is raised? Once after TX FIFO buffer is emptied or always when the TX FIFO buffer is empty?

Hi Vince. I thought the interrupt should only be triggered once but when I use TX FIFIO buffering the interrupt is constantly triggered. If you check the Example_2803xSci_FFDLB_int example you will see that in this case interrupt is constantly triggered.

Hi WW,

The constant triggering only occurs if you do not clear the interrupts. Have you cleared the appropriate interrupts?

Regards,

Vince

Hi Vince. In the Example_2803xSci_FFDLB_int example TX interrupt is constantly triggered even when the lines:

    SciaRegs.SCIFFTX.bit.TXFFINTCLR=1;  // Clear SCI Interrupt flag
    PieCtrlRegs.PIEACK.all|=0x100;      // Issue PIE ACK

are present at the end of TX interrupt.

Hi WW,

Have you checked if other interrupt flags have been set? It sounds like maybe error flags are set.

Regards,

Vince