TMS320F28388D: try to understand the operation for Ethernet MAC controller

Will , 

Will get back to you regarding this query in a couple of days.

Best Regards

Siddharth

Hi Siddharth, 

The below is my new understanding regarding to the EMAC peripheral, I'd like to check with you if it is right or not: 

1). There are only 2 DMA channels but not 4; 

2). Each DMA channel can work in Rx or Tx direction, it is bi-directional. And if Rx request and Tx request simultaneously arrive, the DMA channel will arbitrate according to fixed priority or weighted round-robin priority scheme. 

3). When the 2 DMA channels receive the transfer request (no matter it is Rx or Tx) simultaneously, there will be 3 arbitration schemes can be chosen: fixed priority scheme, WSP and weighted round-robin. 

4). In Rx path, we can set the routing from MAC to queues and the routing from queues to Rx DMA channels. My question is how much Rx FIFO in the system? If only one FIFO, how the queues correspond to Rx FIFO contents? 

Regards, 

Will  

Will, 

Your understanding is correct,  

For the fourth point,  EMAC supports two Rx queues. The Rx FIFO size and Tx fIFO size is specified in the MAC_HW_Feature1 Register. As per the TRM, it is 4096 bytes.  The ROS bits in the MTL_RxQ0_Operation_Mode Register are used to indicate the the size of the allocated Receive queues in blocks of 256 bytes.

Best Regards

Siddharth

Hi Siddharth, 

Thanks for your explanation. It is more clear for me now. 

Regards, 

Will 

Will 

Thanks for the confirmation. Will close this thread.

Best Regards

Siddharth

Hi Siddharth, 

A further question: when forming the unicast packet as below, the first 6 bytes are destination address, I want to check with you if byte-7 and byte-8 are the type/length segment in a MAC frame? 

Best, 

Will